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/openbmc/linux/drivers/clk/socfpga/
H A Dclk.h23 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ argument
24 ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
26 #define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \ argument
27 ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
/openbmc/u-boot/drivers/mmc/
H A Dsocfpga_dw_mmc.c35 unsigned int smplsel; member
55 u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | in socfpga_dwmci_clksel()
62 debug("%s: drvsel %d smplsel %d\n", __func__, in socfpga_dwmci_clksel()
63 priv->drvsel, priv->smplsel); in socfpga_dwmci_clksel()
129 priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), in socfpga_dwmmc_ofdata_to_platdata()
130 "smplsel", 0); in socfpga_dwmmc_ofdata_to_platdata()
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsynopsys-dw-mshc.yaml44 - description: register shift for the smplsel(drive in) setting
50 smplsel(drive in) setting.
/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc-pltfm.c27 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \ argument
28 ((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0))
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_stratix10_socdk.dts85 smplsel = <0>;