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/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
18 The SMMU may also raise interrupts in response to various fault
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
[all …]
H A Dqcom,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konrad.dybcio@linaro.org>
13 Qualcomm "B" family devices which are not compatible with arm-smmu have
16 to non-secure vs secure interrupt line.
21 - items:
22 - enum:
23 - qcom,msm8916-iommu
24 - qcom,msm8953-iommu
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/openbmc/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-qcom.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
12 #include "arm-smmu.h"
13 #include "arm-smmu-qcom.h"
15 #define QCOM_DUMMY_VAL -1
17 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) in to_qcom_smmu() argument
19 return container_of(smmu, struct qcom_smmu, smmu); in to_qcom_smmu()
22 static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page, in qcom_smmu_tlb_sync() argument
28 arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL); in qcom_smmu_tlb_sync()
30 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { in qcom_smmu_tlb_sync()
[all …]
H A Darm-smmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for ARM architected SMMU implementations.
10 * - SMMUv1 and v2 implementations
11 * - Stream-matching and stream-indexing
12 * - v7/v8 long-descriptor format
13 * - Non-secure access to the SMMU
14 * - Context fault reporting
15 * - Extended Stream ID (16 bit)
18 #define pr_fmt(fmt) "arm-smmu: " fmt
24 #include <linux/dma-mapping.h>
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H A Dqcom_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
13 #include <linux/dma-mapping.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
33 #include "arm-smmu.h"
86 if (!fwspec || fwspec->ops != &qcom_iommu_ops) in to_iommu()
94 struct qcom_iommu_dev *qcom_iommu = d->iommu; in to_ctx()
97 return qcom_iommu->ctxs[asid]; in to_ctx()
103 writel_relaxed(val, ctx->base + reg); in iommu_writel()
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/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-a53", "arm,armv8";
27 enable-method = "psci";
28 operating-points-v2 = <&cpu_opp_table>;
30 cpu-idle-states = <&CPU_SLEEP_0>;
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/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
24 #address-cells = <2>;
25 #size-cells = <2>;
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/openbmc/linux/drivers/iommu/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
36 sizes at both stage-1 and stage-2, as well as address spaces
37 up to 48-bits in size.
43 Enable self-tests for LPAE page table allocator. This performs
44 a series of page-table consistency checks during boot.
53 Enable support for the ARM Short-descriptor pagetable format.
54 This supports 32-bit virtual and physical addresses mapped using
55 2-level tables with 4KB pages/1MB sections, and contiguous entries
62 Enable self-tests for ARMv7s page table allocator. This performs
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/interconnect/qcom,sdm660.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/qcom,apr.h>
[all …]
H A Dmsm8998.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/gpio/gpio.h>
13 interrupt-parent = <&intc>;
15 qcom,msm-id = <292 0x0>;
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H A Dmsm8996.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm8996.h>
11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
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H A Dsdx75.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom,rpmhpd.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
19 interrupt-parent = <&intc>;
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H A Dsdm845-cheza.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
25 stdout-path = "serial0:115200n8";
29 compatible = "pwm-backlight";
31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
32 power-supply = <&ppvar_sys>;
33 pinctrl-names = "default";
34 pinctrl-0 = <&ap_edp_bklten>;
37 /* FIXED REGULATORS - parents above children */
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/openbmc/linux/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.c1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/io-pgtable.h>
27 #include <linux/pci-ats.h>
30 #include "arm-smmu-v3.h"
31 #include "../../dma-iommu.h"
32 #include "../../iommu-sva.h"
37 …domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
42 "Disable MSI-based polling for CMD_SYNC completion.");
84 { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
85 { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"},
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/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/openbmc/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dgmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
4 ---
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Rob Clark <robdclark@gmail.com>
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
23 - items:
24 - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu
26 - const: qcom,adreno-gmu-wrapper
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H A Dqcom,mdp5.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
15 - Rob Clark <robdclark@gmail.com>
20 - const: qcom,mdp5
22 - items:
23 - enum:
24 - qcom,apq8084-mdp5
25 - qcom,msm8226-mdp5
[all …]
/openbmc/qemu/hw/arm/
H A Dsmmu-common.c2 * Copyright (C) 2014-2016 Broadcom Corporation
23 #include "hw/qdev-properties.h"
28 #include "qemu/error-report.h"
29 #include "hw/arm/smmu-common.h"
30 #include "smmu-internal.h"
41 a += key->asid + key->vmid + key->level + key->tg; in smmu_iotlb_key_hash()
42 b += extract64(key->iova, 0, 32); in smmu_iotlb_key_hash()
43 c += extract64(key->iova, 32, 32); in smmu_iotlb_key_hash()
51 static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2) in smmu_iotlb_key_equal() argument
53 SMMUIOTLBKey *k1 = (SMMUIOTLBKey *)v1, *k2 = (SMMUIOTLBKey *)v2; in smmu_iotlb_key_equal()
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/openbmc/linux/drivers/perf/
H A Darm_smmuv3_pmu.c1 // SPDX-License-Identifier: GPL-2.0
9 * <phys_addr_page> is the physical page address of the SMMU PMCG wrapped
15 * filter_enable - 0 = no filtering, 1 = filtering enabled
16 * filter_span - 0 = exact match, 1 = pattern match
17 * filter_stream_id - pattern to filter against
19 * To match a partial StreamID where the X most-significant bits must match
20 * but the Y least-significant bits might differ, STREAMID is programmed
22 * STREAMID[Y - 1] == 0.
23 * STREAMID[Y - 2:0] == 1 (where Y > 1).
27 * Example: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1,
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/openbmc/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx65.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/interconnect/qcom,sdx65.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
[all …]

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