Lines Matching +full:smmu +full:- +full:v2
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
86 compatible = "arm,cortex-a57";
88 enable-method = "psci";
89 next-level-cache = <&cluster0_l2>;
94 compatible = "arm,cortex-a57";
96 enable-method = "psci";
97 next-level-cache = <&cluster0_l2>;
102 compatible = "arm,cortex-a57";
104 enable-method = "psci";
105 next-level-cache = <&cluster0_l2>;
110 compatible = "arm,cortex-a57";
112 enable-method = "psci";
113 next-level-cache = <&cluster0_l2>;
118 compatible = "arm,cortex-a57";
120 enable-method = "psci";
121 next-level-cache = <&cluster1_l2>;
126 compatible = "arm,cortex-a57";
128 enable-method = "psci";
129 next-level-cache = <&cluster1_l2>;
134 compatible = "arm,cortex-a57";
136 enable-method = "psci";
137 next-level-cache = <&cluster1_l2>;
142 compatible = "arm,cortex-a57";
144 enable-method = "psci";
145 next-level-cache = <&cluster1_l2>;
150 compatible = "arm,cortex-a57";
152 enable-method = "psci";
153 next-level-cache = <&cluster2_l2>;
158 compatible = "arm,cortex-a57";
160 enable-method = "psci";
161 next-level-cache = <&cluster2_l2>;
166 compatible = "arm,cortex-a57";
168 enable-method = "psci";
169 next-level-cache = <&cluster2_l2>;
174 compatible = "arm,cortex-a57";
176 enable-method = "psci";
177 next-level-cache = <&cluster2_l2>;
182 compatible = "arm,cortex-a57";
184 enable-method = "psci";
185 next-level-cache = <&cluster3_l2>;
190 compatible = "arm,cortex-a57";
192 enable-method = "psci";
193 next-level-cache = <&cluster3_l2>;
198 compatible = "arm,cortex-a57";
200 enable-method = "psci";
201 next-level-cache = <&cluster3_l2>;
206 compatible = "arm,cortex-a57";
208 enable-method = "psci";
209 next-level-cache = <&cluster3_l2>;
212 cluster0_l2: l2-cache0 {
214 cache-level = <2>;
215 cache-unified;
218 cluster1_l2: l2-cache1 {
220 cache-level = <2>;
221 cache-unified;
224 cluster2_l2: l2-cache2 {
226 cache-level = <2>;
227 cache-unified;
230 cluster3_l2: l2-cache3 {
232 cache-level = <2>;
233 cache-unified;
237 gic: interrupt-controller@4d000000 {
238 compatible = "arm,gic-v3";
239 #interrupt-cells = <3>;
240 #address-cells = <2>;
241 #size-cells = <2>;
243 interrupt-controller;
244 #redistributor-regions = <1>;
245 redistributor-stride = <0x0 0x30000>;
253 its_dsa: msi-controller@c6000000 {
254 compatible = "arm,gic-v3-its";
255 msi-controller;
256 #msi-cells = <1>;
262 compatible = "arm,armv8-timer";
270 compatible = "arm,cortex-a57-pmu";
275 compatible = "hisilicon,mbigen-v2";
279 msi-parent = <&its_dsa 0x40080>;
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 num-pins = <2>;
286 msi-parent = <&its_dsa 0x40000>;
287 interrupt-controller;
288 #interrupt-cells = <2>;
289 num-pins = <128>;
293 msi-parent = <&its_dsa 0x40040>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 num-pins = <128>;
300 msi-parent = <&its_dsa 0x40085>;
301 interrupt-controller;
302 #interrupt-cells = <2>;
303 num-pins = <10>;
308 compatible = "hisilicon,mbigen-v2";
312 msi-parent = <&its_dsa 0x40800>;
313 interrupt-controller;
314 #interrupt-cells = <2>;
315 num-pins = <409>;
318 mbigen_sas0: intc-sas0 {
319 msi-parent = <&its_dsa 0x40900>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 num-pins = <128>;
333 * have a SMMU translation for MSI. In order to workaround this,
336 * systems. Hence please make sure that the smmu pcie node on
338 * when iommu-map entry is used along with the PCIe node.
339 * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
342 compatible = "arm,smmu-v3";
344 #iommu-cells = <1>;
345 dma-coherent;
346 hisilicon,broken-prefetch-cmd;
351 compatible = "simple-bus";
352 #address-cells = <2>;
353 #size-cells = <2>;
357 compatible = "hisilicon,hip06-lpc";
358 #size-cells = <1>;
359 #address-cells = <2>;
363 compatible = "ipmi-bt";
371 clock-frequency = <1843200>;
378 compatible = "fixed-clock";
379 clock-frequency = <50000000>;
380 #clock-cells = <0>;
384 compatible = "generic-ohci";
386 interrupt-parent = <&mbigen_usb>;
388 dma-coherent;
393 compatible = "generic-ehci";
395 interrupt-parent = <&mbigen_usb>;
397 dma-coherent;
402 compatible = "hisilicon,peri-subctrl","syscon";
407 compatible = "hisilicon,dsa-subctrl", "syscon";
412 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
422 compatible = "hisilicon,hns-mdio";
424 subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
425 #address-cells = <1>;
426 #size-cells = <0>;
428 phy0: ethernet-phy@0 {
429 compatible = "ethernet-phy-ieee802.3-c22";
433 phy1: ethernet-phy@1 {
434 compatible = "ethernet-phy-ieee802.3-c22";
440 #address-cells = <1>;
441 #size-cells = <0>;
442 compatible = "hisilicon,hns-dsaf-v2";
443 mode = "6port-16rss";
446 reg-names = "ppe-base", "dsaf-base";
447 interrupt-parent = <&mbigen_dsaf0>;
448 subctrl-syscon = <&dsa_subctrl>;
449 reset-field-offset = <0>;
534 desc-num = <0x400>;
535 buf-size = <0x1000>;
536 dma-coherent;
540 serdes-syscon = <&serdes_ctrl>;
541 port-rst-offset = <0>;
542 port-mode-offset = <0>;
543 media-type = "fiber";
548 serdes-syscon = <&serdes_ctrl>;
549 port-rst-offset = <1>;
550 port-mode-offset = <1>;
551 media-type = "fiber";
556 phy-handle = <&phy0>;
557 serdes-syscon = <&serdes_ctrl>;
558 port-rst-offset = <4>;
559 port-mode-offset = <2>;
560 media-type = "copper";
565 phy-handle = <&phy1>;
566 serdes-syscon = <&serdes_ctrl>;
567 port-rst-offset = <5>;
568 port-mode-offset = <3>;
569 media-type = "copper";
573 eth0: ethernet-4 {
574 compatible = "hisilicon,hns-nic-v2";
575 ae-handle = <&dsaf0>;
576 port-idx-in-ae = <4>;
577 local-mac-address = [00 00 00 00 00 00];
579 dma-coherent;
582 eth1: ethernet-5 {
583 compatible = "hisilicon,hns-nic-v2";
584 ae-handle = <&dsaf0>;
585 port-idx-in-ae = <5>;
586 local-mac-address = [00 00 00 00 00 00];
588 dma-coherent;
591 eth2: ethernet-0 {
592 compatible = "hisilicon,hns-nic-v2";
593 ae-handle = <&dsaf0>;
594 port-idx-in-ae = <0>;
595 local-mac-address = [00 00 00 00 00 00];
597 dma-coherent;
600 eth3: ethernet-1 {
601 compatible = "hisilicon,hns-nic-v2";
602 ae-handle = <&dsaf0>;
603 port-idx-in-ae = <1>;
604 local-mac-address = [00 00 00 00 00 00];
606 dma-coherent;
610 compatible = "hisilicon,hip06-sas-v2";
612 sas-addr = [50 01 88 20 16 00 00 00];
613 hisilicon,sas-syscon = <&dsa_subctrl>;
614 ctrl-reset-reg = <0xa60>;
615 ctrl-reset-sts-reg = <0x5a30>;
616 ctrl-clock-ena-reg = <0x338>;
618 queue-count = <16>;
619 phy-count = <8>;
620 dma-coherent;
621 interrupt-parent = <&mbigen_sas0>;
652 compatible = "hisilicon,hip06-sas-v2";
654 sas-addr = [50 01 88 20 16 00 00 00];
655 hisilicon,sas-syscon = <&pcie_subctl>;
656 hip06-sas-v2-quirk-amt;
657 ctrl-reset-reg = <0xa18>;
658 ctrl-reset-sts-reg = <0x5a0c>;
659 ctrl-clock-ena-reg = <0x318>;
661 queue-count = <16>;
662 phy-count = <8>;
663 dma-coherent;
664 interrupt-parent = <&mbigen_sas1>;
695 compatible = "hisilicon,hip06-sas-v2";
697 sas-addr = [50 01 88 20 16 00 00 00];
698 hisilicon,sas-syscon = <&pcie_subctl>;
699 ctrl-reset-reg = <0xae0>;
700 ctrl-reset-sts-reg = <0x5a70>;
701 ctrl-clock-ena-reg = <0x3a8>;
703 queue-count = <16>;
704 phy-count = <9>;
705 dma-coherent;
706 interrupt-parent = <&mbigen_sas2>;
737 compatible = "hisilicon,hip06-pcie-ecam";
740 bus-range = <0 31>;
741 msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
742 msi-map-mask = <0xffff>;
743 #address-cells = <3>;
744 #size-cells = <2>;
746 dma-coherent;
749 #interrupt-cells = <1>;
750 interrupt-map-mask = <0xf800 0 0 7>;
751 interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4