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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmicrel-ksz90x1.txt4 to clock delays. You can specify clock delay values in the PHY OF
8 Note that these settings are applied after any phy-specific fixup from
14 All skew control options are specified in picoseconds. The minimum
17 skew values actually increase in 120ps steps, starting from -840ps. The
23 The following table shows the actual skew delay you will get for each of the
25 corresponding pad skew register:
27 Device Tree Value Delay Pad Skew Register Value
28 -----------------------------------------------------
29 0 -840ps 0000
30 200 -720ps 0001
[all …]
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dmicrel-ksz90x1.txt4 clock delays. You can specify clock delay values by adding
5 micrel-specific properties to an Ethernet OF device node.
7 Note that these settings are applied after any phy-specific fixup from
13 All skew control options are specified in picoseconds. The minimum
19 - rxc-skew-ps : Skew control of RXC pad
20 - rxdv-skew-ps : Skew control of RX CTL pad
21 - txc-skew-ps : Skew control of TXC pad
22 - txen-skew-ps : Skew control of TX CTL pad
23 - rxd0-skew-ps : Skew control of RX data 0 pad
24 - rxd1-skew-ps : Skew control of RX data 1 pad
[all …]
/openbmc/linux/arch/arm/boot/dts/gemini/
H A Dgemini-sl93512r.dts1 // SPDX-License-Identifier: GPL-2.0
5 * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor.
9 /dts-v1/;
12 #include <dt-bindings/input/input.h>
15 model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD";
17 #address-cells = <1>;
18 #size-cells = <1>;
28 stdout-path = &uart0;
32 compatible = "gpio-keys";
34 button-wps {
[all …]
H A Dgemini-sq201.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
30 button-setup {
31 debounce-interval = <100>;
32 wakeup-source;
[all …]
H A Dgemini-nas4220b.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for the Gemini-based Raidsonic NAS IB-4220-B
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
12 model = "Raidsonic NAS IB-4220-B";
13 compatible = "raidsonic,ib-4220-b", "cortina,gemini";
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
[all …]
H A Dgemini-dlink-dns-313.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/thermal/thermal.h>
13 model = "D-Link DNS-313 1-Bay Network Storage Enclosure";
14 compatible = "dlink,dns-313", "cortina,gemini";
15 #address-cells = <1>;
16 #size-cells = <1>;
19 /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */
[all …]
/openbmc/u-boot/board/xes/xpedite537x/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0+
20 * There are four board-specific SDRAM timing parameters which must be
22 * 1.) CPO (Read Capture Delay)
23 * - TIMING_CFG_2 register
25 * chip-specific internal delays.
26 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
27 * - TIMING_CFG_2 register
31 * of 1/2 clock delay.
33 * - DDR_SDRAM_CLK_CNTL register
36 * - TIMING_CFG_2 register
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_cyclone5_vining_fpga.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
12 compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
34 gpio-keys {
35 compatible = "gpio-keys";
68 regulator-usb-nrst {
69 compatible = "regulator-fixed";
70 regulator-name = "usb_nrst";
[all …]
H A Dsocfpga_arria10_socdk.dtsi1 // SPDX-License-Identifier: GPL-2.0+
9 compatible = "altr,socfpga-arria10-socdk", "altr,socfpga-arria10", "altr,socfpga";
18 stdout-path = "serial0:115200n8";
28 compatible = "gpio-leds";
31 label = "a10sr-led0";
36 label = "a10sr-led1";
41 label = "a10sr-led2";
46 label = "a10sr-led3";
51 ref_033v: 033-v-ref {
52 compatible = "regulator-fixed";
[all …]
H A Dsocfpga_cyclone5_sodia.dts1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
12 compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
30 compatible = "regulator-fixed";
31 regulator-name = "3.3V";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
36 leds: gpio-leds {
[all …]
H A Dsocfpga_arria5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "altr,socfpga-arria5-socdk", "altr,socfpga-arria5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
32 led-hps0 {
37 led-hps1 {
42 led-hps2 {
47 led-hps3 {
54 compatible = "regulator-fixed";
55 regulator-name = "3.3V";
[all …]
H A Dsocfpga_cyclone5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
32 led-hps0 {
37 led-hps1 {
42 led-hps2 {
47 led-hps3 {
54 compatible = "regulator-fixed";
55 regulator-name = "3.3V";
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp15xx-dhcor-testbench.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
17 stdout-path = "serial0:115200n8";
20 sd_switch: regulator-sd_switch {
21 compatible = "regulator-gpio";
22 regulator-name = "sd_switch";
23 regulator-min-microvolt = <1800000>;
24 regulator-max-microvolt = <2900000>;
25 regulator-type = "voltage";
26 regulator-always-on;
29 gpios-states = <0>;
[all …]
H A Dstm32mp15xx-dhcor-drc-compact.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
21 stdout-path = "serial0:115200n8";
25 compatible = "gpio-leds";
29 default-state = "off";
35 default-state = "off";
40 compatible = "regulator-fixed";
41 regulator-name = "vio";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
45 regulator-always-on;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_cyclone5_vining_fpga.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
12 compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
34 gpio-keys {
35 compatible = "gpio-keys";
56 regulator-usb-nrst {
57 compatible = "regulator-fixed";
58 regulator-name = "usb_nrst";
[all …]
H A Dsocfpga_arria10_socdk.dtsi21 compatible = "altr,socfpga-arria10", "altr,socfpga";
31 stdout-path = "serial0:115200n8";
38 u-boot,dm-pre-reloc;
42 compatible = "gpio-leds";
45 label = "a10sr-led0";
50 label = "a10sr-led1";
55 label = "a10sr-led2";
60 label = "a10sr-led3";
66 u-boot,dm-pre-reloc;
71 phy-mode = "rgmii";
[all …]
H A Dsocfpga_arria5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "altr,socfpga-arria5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
53 regulator_3_3v: 3-3-v-regulator {
54 compatible = "regulator-fixed";
55 regulator-name = "3.3V";
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
63 phy-mode = "rgmii";
[all …]
H A Dsocfpga_cyclone5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
53 regulator_3_3v: 3-3-v-regulator {
54 compatible = "regulator-fixed";
55 regulator-name = "3.3V";
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
67 phy-mode = "rgmii";
[all …]
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_n5x_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,n5x-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
29 sdram_edac: memory-controller@f87f8000 {
30 compatible = "snps,ddrc-3.80a";
39 compatible = "intel,easic-n5x-clkmgr";
44 phy-mode = "rgmii";
45 phy-handle = <&phy0>;
47 max-frame-size = <9000>;
50 #address-cells = <1>;
[all …]
H A Dsocfpga_agilex_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
23 compatible = "gpio-leds";
53 phy-mode = "rgmii";
54 phy-handle = <&phy0>;
56 max-frame-size = <9000>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 compatible = "snps,dwmac-mdio";
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-emcon.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/pwm/pwm.h>
8 #include <dt-bindings/input/input.h>
12 model = "emtrion SoM emCON-MX6";
13 compatible = "emtrion,emcon-mx6";
23 stdout-path = &uart1;
31 gpio-keys {
32 compatible = "gpio-keys";
33 pinctrl-names = "default";
[all …]
H A Dimx6q-novena.dts2 * Copyright 2015 Sutajio Ko-Usagi PTE LTD
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
49 /dts-v1/;
51 #include <dt-bindings/gpio/gpio.h>
52 #include <dt-bindings/input/input.h>
56 compatible = "kosagi,imx6q-novena", "fsl,imx6q";
65 stdout-path = &uart2;
69 compatible = "pwm-backlight";
71 pinctrl-names = "default";
[all …]
/openbmc/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10_socdk_nand.dts1 // SPDX-License-Identifier: GPL-2.0-only
10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
25 led-hps0 {
30 led-hps1 {
35 led-hps2 {
47 ref_033v: regulator-v-ref {
48 compatible = "regulator-fixed";
49 regulator-name = "0.33V";
[all …]
H A Dsocfpga_stratix10_socdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
25 led-hps0 {
30 led-hps1 {
35 led-hps2 {
47 ref_033v: regulator-v-ref {
48 compatible = "regulator-fixed";
49 regulator-name = "0.33V";
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c1 // SPDX-License-Identifier: GPL-2.0
41 /* Temp array for skew data storage */
80 * Array to hold the total sum of skew from all iterations in ddr3_pbs_tx()
86 * Array to hold the total average skew from both patterns in ddr3_pbs_tx()
92 /* bit array for unlock pups - used to repeat on the RX operation */ in ddr3_pbs_tx()
102 DEBUG_PBS_S("DDR3 - PBS TX - Starting PBS TX procedure\n"); in ddr3_pbs_tx()
104 pups = dram_info->num_of_total_pups; in ddr3_pbs_tx()
105 max_pup = dram_info->num_of_total_pups; in ddr3_pbs_tx()
110 /* [0] = 1 - Enable SW override */ in ddr3_pbs_tx()
111 /* 0x15B8 - Training SW 2 Register */ in ddr3_pbs_tx()
[all …]

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