Lines Matching +full:skew +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0
41 /* Temp array for skew data storage */
80 * Array to hold the total sum of skew from all iterations in ddr3_pbs_tx()
86 * Array to hold the total average skew from both patterns in ddr3_pbs_tx()
92 /* bit array for unlock pups - used to repeat on the RX operation */ in ddr3_pbs_tx()
102 DEBUG_PBS_S("DDR3 - PBS TX - Starting PBS TX procedure\n"); in ddr3_pbs_tx()
104 pups = dram_info->num_of_total_pups; in ddr3_pbs_tx()
105 max_pup = dram_info->num_of_total_pups; in ddr3_pbs_tx()
110 /* [0] = 1 - Enable SW override */ in ddr3_pbs_tx()
111 /* 0x15B8 - Training SW 2 Register */ in ddr3_pbs_tx()
113 DEBUG_PBS_S("DDR3 - PBS RX - SW Override Enabled\n"); in ddr3_pbs_tx()
116 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_pbs_tx()
118 /* Running twice for 2 different patterns. each patterns - 3 times */ in ddr3_pbs_tx()
120 DEBUG_PBS_C("DDR3 - PBS TX - Working with pattern - ", in ddr3_pbs_tx()
135 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); ecc++) { in ddr3_pbs_tx()
139 * num - ecc mode dependent - 4-8 / 1 pups in ddr3_pbs_tx()
141 cur_max_pup = (1 - ecc) * in ddr3_pbs_tx()
142 dram_info->num_of_std_pups + ecc; in ddr3_pbs_tx()
148 /* 64 bit - 8 pups */ in ddr3_pbs_tx()
151 /* 32 bit - 4 pups */ in ddr3_pbs_tx()
154 /* 16 bit - 2 pups */ in ddr3_pbs_tx()
158 /* ECC Support - Switch ECC Mux on ecc=1 */ in ddr3_pbs_tx()
161 reg |= (dram_info->ecc_ena * ecc << in ddr3_pbs_tx()
166 DEBUG_PBS_S("DDR3 - PBS Tx - ECC Mux Enabled\n"); in ddr3_pbs_tx()
168 DEBUG_PBS_S("DDR3 - PBS Tx - ECC Mux Disabled\n"); in ddr3_pbs_tx()
176 (max_pup - 1)][dq] = in ddr3_pbs_tx()
191 DEBUG_PBS_S("DDR3 - PBS Tx - Pbs Rep Loop is "); in ddr3_pbs_tx()
198 DEBUG_PBS_S("DDR3 - PBS Tx - Set all PBS values to MIN\n"); in ddr3_pbs_tx()
204 (1 - ecc) + in ddr3_pbs_tx()
206 [dq], CS0, (1 - ecc) * in ddr3_pbs_tx()
215 DEBUG_PBS_S("DDR3 - PBS Tx - ADLL shift right one phase before fail\n"); in ddr3_pbs_tx()
223 DEBUG_PBS_S("DDR3 - PBS Tx - perform PBS for each bit\n"); in ddr3_pbs_tx()
226 * In this stage - start_over = 0 in ddr3_pbs_tx()
238 DEBUG_PBS_S("DDR3 - PBS Tx - FAIL - Adll reach max value\n"); in ddr3_pbs_tx()
242 DEBUG_PBS_FULL_C("DDR3 - PBS TX - values for iteration - ", in ddr3_pbs_tx()
246 * To minimize delay elements, inc in ddr3_pbs_tx()
249 DEBUG_PBS_S("DDR3 - PBS - PUP"); in ddr3_pbs_tx()
254 /* Set skew value for all dq */ in ddr3_pbs_tx()
256 * Bit# Deskew <- Bit# Deskew - in ddr3_pbs_tx()
259 * (minimize delay elements) in ddr3_pbs_tx()
263 DEBUG_PBS_S("-"); in ddr3_pbs_tx()
278 skew_sum_array[pup + (ecc * (max_pup - 1))] in ddr3_pbs_tx()
284 /* ECC Support - Disable ECC MUX */ in ddr3_pbs_tx()
291 DEBUG_PBS_C("DDR3 - PBS TX - values for current pattern - ", in ddr3_pbs_tx()
295 * To minimize delay elements, inc from pbs value the in ddr3_pbs_tx()
298 DEBUG_PBS_S("DDR3 - PBS - PUP"); in ddr3_pbs_tx()
303 /* set skew value for all dq */ in ddr3_pbs_tx()
304 …/* Bit# Deskew <- Bit# Deskew - last / first failing bit Deskew For all bits (per PUP) (minimize … in ddr3_pbs_tx()
307 DEBUG_PBS_S("-"); in ddr3_pbs_tx()
316 * Calculate the average skew for current pattern for each in ddr3_pbs_tx()
319 DEBUG_PBS_C("DDR3 - PBS TX - Average for pattern - ", in ddr3_pbs_tx()
325 * pattern skew array in ddr3_pbs_tx()
336 /* Calculate the average skew */ in ddr3_pbs_tx()
343 DEBUG_PBS_S("DDR3 - PBS TX - Average for all patterns:\n"); in ddr3_pbs_tx()
346 * To minimize delay elements, inc from pbs value the min in ddr3_pbs_tx()
349 DEBUG_PBS_S("DDR3 - PBS - PUP"); in ddr3_pbs_tx()
354 /* Set skew value for all dq */ in ddr3_pbs_tx()
356 * Bit# Deskew <- Bit# Deskew - last / first in ddr3_pbs_tx()
358 * (minimize delay elements) in ddr3_pbs_tx()
362 DEBUG_PBS_S("-"); in ddr3_pbs_tx()
371 if (pup == (max_pup - 1) && dram_info->ecc_ena) in ddr3_pbs_tx()
379 /* Disable SW override - Must be in a different stage */ in ddr3_pbs_tx()
380 /* [0]=0 - Enable SW override */ in ddr3_pbs_tx()
383 /* 0x15B8 - Training SW 2 Register */ in ddr3_pbs_tx()
390 DEBUG_PBS_S("DDR3 - PBS Tx - PBS TX ended successfuly\n"); in ddr3_pbs_tx()
416 switch (dram_info->ddr_width) { in ddr3_tx_shift_dqs_adll_step_before_fail()
438 cur_max_pup = dram_info->num_of_std_pups; in ddr3_tx_shift_dqs_adll_step_before_fail()
448 * Increment (Move to right - ADLL) DQ TX delay in ddr3_tx_shift_dqs_adll_step_before_fail()
453 pup * (1 - ecc) + in ddr3_tx_shift_dqs_adll_step_before_fail()
459 /* 0 - all locked */ in ddr3_tx_shift_dqs_adll_step_before_fail()
479 * Decrement (Move Back to Left two steps - ADLL) in ddr3_tx_shift_dqs_adll_step_before_fail()
480 * DQ TX delay for current failed pups and save in ddr3_tx_shift_dqs_adll_step_before_fail()
485 dqs_dly_set[pup] = adll_val - 1; in ddr3_tx_shift_dqs_adll_step_before_fail()
491 DEBUG_PBS_FULL_S("DDR3 - PBS Tx - Shift DQ - Adll value reached maximum\n"); in ddr3_tx_shift_dqs_adll_step_before_fail()
496 dqs_dly_set[pup] = adll_val - 1; in ddr3_tx_shift_dqs_adll_step_before_fail()
501 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
505 ddr3_pbs_write_pup_dqs_reg(CS0, pup * (1 - ecc) + ECC_PUP * ecc, in ddr3_tx_shift_dqs_adll_step_before_fail()
522 * Array to hold the total sum of skew from all iterations in ddr3_pbs_rx()
528 * Array to hold the total average skew from both patterns in ddr3_pbs_rx()
534 /* bit array for unlock pups - used to repeat on the RX operation */ in ddr3_pbs_rx()
545 DEBUG_PBS_S("DDR3 - PBS RX - Starting PBS RX procedure\n"); in ddr3_pbs_rx()
547 pups = dram_info->num_of_total_pups; in ddr3_pbs_rx()
548 max_pup = dram_info->num_of_total_pups; in ddr3_pbs_rx()
553 /* [0] = 1 - Enable SW override */ in ddr3_pbs_rx()
554 /* 0x15B8 - Training SW 2 Register */ in ddr3_pbs_rx()
556 DEBUG_PBS_FULL_S("DDR3 - PBS RX - SW Override Enabled\n"); in ddr3_pbs_rx()
559 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_pbs_rx()
561 /* Running twice for 2 different patterns. each patterns - 3 times */ in ddr3_pbs_rx()
563 DEBUG_PBS_FULL_C("DDR3 - PBS RX - Working with pattern - ", in ddr3_pbs_rx()
578 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); ecc++) { in ddr3_pbs_rx()
581 * num - ecc mode dependent - 4-8 / 1 pups in ddr3_pbs_rx()
583 cur_max_pup = (1 - ecc) * in ddr3_pbs_rx()
584 dram_info->num_of_std_pups + ecc; in ddr3_pbs_rx()
590 /* 64 bit - 8 pups */ in ddr3_pbs_rx()
593 /* 32 bit - 4 pups */ in ddr3_pbs_rx()
596 /* 16 bit - 2 pups */ in ddr3_pbs_rx()
600 /* ECC Support - Switch ECC Mux on ecc=1 */ in ddr3_pbs_rx()
603 reg |= (dram_info->ecc_ena * ecc << in ddr3_pbs_rx()
608 DEBUG_PBS_FULL_S("DDR3 - PBS Rx - ECC Mux Enabled\n"); in ddr3_pbs_rx()
610 DEBUG_PBS_FULL_S("DDR3 - PBS Rx - ECC Mux Disabled\n"); in ddr3_pbs_rx()
617 pup + ecc * (max_pup - 1)][dq] = in ddr3_pbs_rx()
632 DEBUG_PBS_FULL_S("DDR3 - PBS Rx - Pbs Rep Loop is "); in ddr3_pbs_rx()
644 pup * (1 - ecc) in ddr3_pbs_rx()
662 DEBUG_PBS_FULL_S("DDR3 - PBS Rx - Shift RX DQS to first fail\n"); in ddr3_pbs_rx()
668 DEBUG_PBS_S("DDR3 - PBS Rx - ddr3_rx_shift_dqs_to_first_fail failed.\n"); in ddr3_pbs_rx()
670 DEBUG_PBS_S("\nDDR3 - PBS Rx - SKIP.\n"); in ddr3_pbs_rx()
676 /* 0x15B0 - Training Register */ in ddr3_pbs_rx()
682 /* [0] = 1 - Enable SW override, [4] = 1 - FIFO reset */ in ddr3_pbs_rx()
683 /* 0x15B8 - Training SW 2 Register */ in ddr3_pbs_rx()
694 /* 0x15B0 - Training Register */ in ddr3_pbs_rx()
715 [pup * (1 - ecc) + in ddr3_pbs_rx()
726 DEBUG_PBS_FULL_S("DDR3 - PBS Rx - perform PBS for each bit\n"); in ddr3_pbs_rx()
727 /* in this stage - start_over = 0; */ in ddr3_pbs_rx()
732 DEBUG_PBS_S("DDR3 - PBS Rx - ddr3_pbs_per_bit failed."); in ddr3_pbs_rx()
741 DEBUG_PBS_FULL_S("DDR3 - PBS Rx - FAIL - Algorithm failed doing RX PBS\n"); in ddr3_pbs_rx()
745 /* Return DQS ADLL to default value - 15 */ in ddr3_pbs_rx()
752 DEBUG_PBS_FULL_C("DDR3 - PBS RX - values for iteration - ", in ddr3_pbs_rx()
756 * To minimize delay elements, inc from in ddr3_pbs_rx()
759 DEBUG_PBS_FULL_S("DDR3 - PBS - PUP"); in ddr3_pbs_rx()
765 /* Set skew value for all dq */ in ddr3_pbs_rx()
767 * Bit# Deskew <- Bit# Deskew - in ddr3_pbs_rx()
770 * (minimize delay elements) in ddr3_pbs_rx()
774 DEBUG_PBS_FULL_S("-"); in ddr3_pbs_rx()
791 [pup + (ecc * (max_pup - 1))] in ddr3_pbs_rx()
797 /* ECC Support - Disable ECC MUX */ in ddr3_pbs_rx()
805 * Calculate the average skew for current pattern for each in ddr3_pbs_rx()
808 DEBUG_PBS_FULL_C("DDR3 - PBS RX - Average for pattern - ", in ddr3_pbs_rx()
813 * current pattern skew array in ddr3_pbs_rx()
823 DEBUG_PBS_C("DDR3 - PBS RX - values for current pattern - ", in ddr3_pbs_rx()
827 * To minimize delay elements, inc from pbs value the in ddr3_pbs_rx()
830 DEBUG_PBS_S("DDR3 - PBS RX - PUP"); in ddr3_pbs_rx()
835 /* Set skew value for all dq */ in ddr3_pbs_rx()
837 * Bit# Deskew <- Bit# Deskew - last / first in ddr3_pbs_rx()
839 * (minimize delay elements) in ddr3_pbs_rx()
843 DEBUG_PBS_S("-"); in ddr3_pbs_rx()
852 /* Calculate the average skew */ in ddr3_pbs_rx()
859 DEBUG_PBS_S("DDR3 - PBS RX - Average for all patterns:\n"); in ddr3_pbs_rx()
862 * To minimize delay elements, inc from pbs value the in ddr3_pbs_rx()
865 DEBUG_PBS_S("DDR3 - PBS - PUP"); in ddr3_pbs_rx()
870 /* Set skew value for all dq */ in ddr3_pbs_rx()
872 * Bit# Deskew <- Bit# Deskew - last / first in ddr3_pbs_rx()
874 * (minimize delay elements) in ddr3_pbs_rx()
878 DEBUG_PBS_S("-"); in ddr3_pbs_rx()
891 /* Disable SW override - Must be in a different stage */ in ddr3_pbs_rx()
892 /* [0]=0 - Enable SW override */ in ddr3_pbs_rx()
895 /* 0x15B8 - Training SW 2 Register */ in ddr3_pbs_rx()
902 DEBUG_PBS_FULL_S("DDR3 - PBS RX - ended successfuly\n"); in ddr3_pbs_rx()
927 switch (dram_info->ddr_width) { in ddr3_rx_shift_dqs_to_first_fail()
949 cur_max_pup = dram_info->num_of_std_pups; in ddr3_rx_shift_dqs_to_first_fail()
953 DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - Starting...\n"); in ddr3_rx_shift_dqs_to_first_fail()
956 DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - Set DQS ADLL to Max for all PUPs\n"); in ddr3_rx_shift_dqs_to_first_fail()
971 …DEBUG_PBS_S("DDR3 - PBS Rx - Shift DQS - MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_SRAM_CMP(ddr3_sdram_co… in ddr3_rx_shift_dqs_to_first_fail()
978 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 DEBUG_PBS_S("DDR3 - PBS Rx - Shift DQS - fail on start with first deskew value\n"); in ddr3_rx_shift_dqs_to_first_fail()
997 DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - DQS deskew reached maximum value\n"); in ddr3_rx_shift_dqs_to_first_fail()
1002 DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - Inc DQS deskew for PUPs: "); in ddr3_rx_shift_dqs_to_first_fail()
1006 /* Increment DQS deskew elements - Only for unlocked pups */ in ddr3_rx_shift_dqs_to_first_fail()
1017 DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - ADLL shift one step before fail\n"); in ddr3_rx_shift_dqs_to_first_fail()
1029 …DEBUG_PBS_S("DDR3 - PBS Rx - Shift DQS - MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_SRAM_CMP(ddr3_sdram_co… in ddr3_rx_shift_dqs_to_first_fail()
1041 DEBUG_PBS_FULL_C(", Set ADLL value = ", (adll_val - 2), 2); in ddr3_rx_shift_dqs_to_first_fail()
1048 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 DEBUG_PBS_FULL_S("DDR3 - PBS Rx - Shift DQS - Adll reach min value\n"); in ddr3_rx_shift_dqs_to_first_fail()
1067 * Decrement (Move Back to Left one phase - ADLL) dqs RX delay in ddr3_rx_shift_dqs_to_first_fail()
1069 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
1093 DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - Lock PBS value for all remaining PUPs bits, pup "); in lock_pups()
1097 idx = pup * (1 - ecc) + ecc * ECC_PUP; in lock_pups()
1122 * Desc: Execute the Per Bit Skew phase.
1133 * ' CHIP-ONLY! - Implementation Limitation '
1164 /* Set init values for retry array - 8 retry */ in ddr3_pbs_per_bit()
1173 DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - Started\n"); in ddr3_pbs_per_bit()
1191 max_pup = dram_info->num_of_std_pups; in ddr3_pbs_per_bit()
1194 /* Increment/ decrement PBS for un-lock bits only */ in ddr3_pbs_per_bit()
1198 pbs_curr_val--; in ddr3_pbs_per_bit()
1200 /* Set Current PBS delay */ in ddr3_pbs_per_bit()
1204 DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - All pups are locked for DQ "); in ddr3_pbs_per_bit()
1213 idx = pup * (1 - ecc) + ecc * ECC_PUP; in ddr3_pbs_per_bit()
1231 * Write Read and compare results - run the test in ddr3_pbs_per_bit()
1255 DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - PbsCurrVal: "); in ddr3_pbs_per_bit()
1261 DEBUG_PBS_FULL_S(" - failed\n"); in ddr3_pbs_per_bit()
1284 /* If all PUPS are locked in all DQ - Break */ in ddr3_pbs_per_bit()
1288 DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - All bit in all pups are successfully locked\n"); in ddr3_pbs_per_bit()
1294 DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - PBS deskew elements reach max\n"); in ddr3_pbs_per_bit()
1295 /* CHIP-ONLY! - Implementation Limitation */ in ddr3_pbs_per_bit()
1299 DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - StartOver: "); in ddr3_pbs_per_bit()
1314 DEBUG_PBS_FULL_C("DDR3 - PBS Per bit - skipping lock of pup (first loop of pbs)", in ddr3_pbs_per_bit()
1320 …DEBUG_PBS_FULL_C("DDR3 - PBS Per bit - Locking pup %d (even though it wasn't supposed to be locked… in ddr3_pbs_per_bit()
1326 DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - Locking remaning DQs for pup - "); in ddr3_pbs_per_bit()
1346 * Reset this pup bit - when in ddr3_pbs_per_bit()
1354 DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - Pup "); in ddr3_pbs_per_bit()
1356 DEBUG_PBS_FULL_C(" is not set in puplocked - ", in ddr3_pbs_per_bit()
1363 DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - false fail - returning to start\n"); in ddr3_pbs_per_bit()
1378 DEBUG_PBS_FULL_C("DDR3 - PBS Per bit - First fail in pup ", in ddr3_pbs_per_bit()
1386 /* TX - inc pbs */ in ddr3_pbs_per_bit()
1387 calc_pbs_diff = pbs_curr_val - in ddr3_pbs_per_bit()
1390 /* RX - dec pbs */ in ddr3_pbs_per_bit()
1391 calc_pbs_diff = first_fail[pup] - in ddr3_pbs_per_bit()
1424 max_pup = dram_info->num_of_total_pups; in ddr3_set_pbs_results()
1425 DEBUG_PBS_FULL_S("DDR3 - PBS - ddr3_set_pbs_results:\n"); in ddr3_set_pbs_results()
1429 if (pup == (max_pup - 1) && dram_info->ecc_ena) in ddr3_set_pbs_results()
1435 * To minimize delay elements, inc from pbs value the min in ddr3_set_pbs_results()
1448 pbs_max -= pbs_min; in ddr3_set_pbs_results()
1450 DEBUG_PBS_FULL_S("DDR3 - PBS - PUP"); in ddr3_set_pbs_results()
1462 /* Set skew value for all dq */ in ddr3_set_pbs_results()
1464 * Bit# Deskew <- Bit# Deskew - last / first in ddr3_set_pbs_results()
1466 * (minimize delay elements) in ddr3_set_pbs_results()
1471 DEBUG_PBS_FULL_S("-"); in ddr3_set_pbs_results()
1472 DEBUG_PBS_FULL_D((skew_array[(pup * DQ_NUM) + dq] - in ddr3_set_pbs_results()
1485 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1488 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()
1509 u32 reg, delay; in ddr3_pbs_write_pup_dqs_reg() local
1512 delay = reg & PUP_DELAY_MASK; in ddr3_pbs_write_pup_dqs_reg()
1513 reg |= ((dqs_delay + delay) << REG_PHY_DQS_REF_DLY_OFFS); in ddr3_pbs_write_pup_dqs_reg()
1537 switch (dram_info->ddr_width) { in ddr3_load_pbs_patterns()
1560 if (dram_info->cs_ena & (1 << cs)) { in ddr3_load_pbs_patterns()
1563 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_load_pbs_patterns()