Searched +full:sgmii +full:- +full:ref +full:- +full:clock +full:- +full:output +full:- +full:enable (Results 1 – 17 of 17) sorted by relevance
/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - $ref: ethernet-controller.yaml# 14 - Andrew Davis <afd@ti.com> 18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX 19 and 1000BASE-T Ethernet protocols. 34 nvmem-cells: 40 nvmem-cell-names: 42 - const: io_impedance_ctrl [all …]
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/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/ |
H A D | high_speed_env_spec.c | 1 // SPDX-License-Identifier: GPL-2.0 24 * serdes_seq_db - holds all serdes sequences, their size and the 30 #define ENDED_OK "High speed PHY - Ended Successfully\n" 63 /* Selector mapping for A380-A0 and A390-Z1 */ 144 * SATA and SGMII 158 /* Rx clk and Tx clk select non-inverted mode */ 177 /* Rx clk and Tx clk select non-inverted mode */ 185 /* SATA and SGMII - power up seq */ 188 * unit_base_reg, unit_offset, mask, SATA data, SGMII data, 198 /* Ref clock source select */ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | phy-cadence-torrent.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 13 such as PCIe, USB, SGMII, QSGMII etc. 16 - Swapnil Jakhade <sjakhade@cadence.com> 17 - Yuti Amonkar <yamonkar@cadence.com> 22 - cdns,torrent-phy 23 - ti,j721e-serdes-10g 25 '#address-cells': [all …]
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/openbmc/linux/drivers/net/phy/ |
H A D | dp83867.c | 1 // SPDX-License-Identifier: GPL-2.0 17 #include <linux/nvmem-consumer.h> 19 #include <dt-bindings/net/ti-dp83867.h> 194 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol() 201 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol() 206 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol() 207 mac = (const u8 *)ndev->dev_addr; in dp83867_set_wol() 210 return -EINVAL; in dp83867_set_wol() 224 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol() 226 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol() [all …]
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/openbmc/u-boot/drivers/phy/marvell/ |
H A D | comphy_a3700.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2015-2016 Marvell International Ltd. 67 /*-----------------------------------------------------------*/ 144 for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) { in comphy_poll_reg() 172 * 1. Enable max PLL. in comphy_pcie_power_up() 192 * 5. Enable idle sync in comphy_pcie_power_up() 197 * 6. Enable the output of 100M/125M/500M clock in comphy_pcie_power_up() 203 * 7. Enable TX in comphy_pcie_power_up() 286 * 1. Select 40-bit data width width in comphy_sata_power_up() 291 * 2. Select reference clock and PHY mode (SATA) in comphy_sata_power_up() [all …]
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H A D | comphy_cp110.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2015-2016 Marvell International Ltd. 31 * For CP-110 we have 2 Selector registers "PHY Selectors", 78 } while (data != val && --usec_timout > 0); in polling_with_timeout() 100 * Add SAR (Sample-At-Reset) configuration for the PCIe clock in comphy_pcie_power_up() 102 * U-Boot to mainline version. in comphy_pcie_power_up() 104 * SerDes Lane 4/5 got the PCIe ref-clock #1, in comphy_pcie_power_up() 105 * and SerDes Lane 0 got PCIe ref-clock #0 in comphy_pcie_power_up() 107 debug("PCIe clock = %x\n", pcie_clk); in comphy_pcie_power_up() 111 /* enable PCIe by4 and by2 */ in comphy_pcie_power_up() [all …]
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/openbmc/linux/drivers/phy/marvell/ |
H A D | phy-mvebu-a3700-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0 11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart. 41 * since the registers are 16-bit. 184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) 189 * (used only by SGMII code) 210 * (used only by SGMII code) 301 /*-----------------------------------------------------------*/ 392 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); in comphy_set_indirect() 393 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, in comphy_set_indirect() 400 if (lane->id == 2) { in comphy_lane_reg_set() [all …]
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/openbmc/linux/arch/arm64/boot/dts/qcom/ |
H A D | sa8775p.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 6 #include <dt-bindings/interconnect/qcom,icc.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/clock/qcom,rpmh.h> 9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h> 10 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 11 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 12 #include <dt-bindings/mailbox/qcom-ipcc.h> 13 #include <dt-bindings/power/qcom-rpmpd.h> 14 #include <dt-bindings/soc/qcom,rpmh-rsc.h> [all …]
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/openbmc/linux/drivers/phy/cadence/ |
H A D | phy-cadence-torrent.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/phy/phy-cadence.h> 12 #include <linux/clk-provider.h> 239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver", 240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der", 241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec", 464 for (i = 0; i < tbl->num_entries; i++) { in cdns_torrent_get_tbl_vals() 465 if (tbl->entries[i].key == key) in cdns_torrent_get_tbl_vals() 466 return tbl->entries[i].vals; in cdns_torrent_get_tbl_vals() [all …]
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/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/ |
H A D | high_speed_env_lib.c | 1 // SPDX-License-Identifier: GPL-2.0 17 #define ENDED_OK "High speed PHY - Ended Successfully\n" 192 return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val]; in board_serdes_cfg_get() 213 return (info->line0_7 >> (line_num << 2)) & 0xF; in get_line_cfg() 215 return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF; in get_line_cfg() 235 * non-established PCIe links (link down). Especially under certain 237 * To enable a board-specific detection pulse width this weak 239 * overwritten if needed by a board-specific version. If the board 240 * code does not provide a non-weak version of this variable, the 286 DEBUG_INIT_S("High speed PHY - Version: "); in serdes_phy_config() [all …]
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/openbmc/linux/drivers/net/ethernet/marvell/ |
H A D | sky2.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 30 /* Yukon-2 */ 32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */ 33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */ 34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */ 35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */ 36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */ 37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */ 38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */ 42 PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */ [all …]
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/openbmc/linux/drivers/net/ethernet/sfc/siena/ |
H A D | mcdi_pcol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 4 * Copyright 2009-2018 Solarflare Communications Inc. 5 * Copyright 2019-2020 Xilinx Inc. 13 /* Power-on reset state */ 35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 38 /* The rest of these are firmware-defined */ 46 /* Values to be written to the per-port status dword in shared 71 * | | \--- Response 72 * | \------- Error 73 * \------------------------------ Resync (always set) [all …]
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/openbmc/linux/drivers/net/ethernet/sfc/ |
H A D | mcdi_pcol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 4 * Copyright 2009-2018 Solarflare Communications Inc. 5 * Copyright 2019-2020 Xilinx Inc. 13 /* Power-on reset state */ 35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 38 /* The rest of these are firmware-defined */ 46 /* Values to be written to the per-port status dword in shared 71 * | | \--- Response 72 * | \------- Error 73 * \------------------------------ Resync (always set) [all …]
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/openbmc/linux/ |
H A D | opengrok0.0.log | 1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz' 2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz' 3 2024-12-2 [all...] |
H A D | opengrok1.0.log | 1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' 2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms) 3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa [all...] |
/openbmc/ |
D | opengrok1.0.log | 1 2025-01-07 03:00:34.968-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler 2 2025-01-07 03:00:35.081-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, - [all...] |
D | opengrok2.0.log | 1 2025-01-06 03:00:36.640-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler 2 2025-01-06 03:00:36.753-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, - [all...] |