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/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear310-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear310-evb", "st,spear310";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
28 st,pins = "gpio0_pin0_grp",
37 st,pins = "i2c0_grp";
41 st,pins = "mii0_grp";
[all …]
H A Dspear320-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear320-evb", "st,spear320";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 st,pinmux-mode = <4>;
24 pinctrl-names = "default";
25 pinctrl-0 = <&state_default>;
29 st,pins = "i2c0_grp";
33 st,pins = "mii0_grp";
[all …]
H A Dspear320-hmi.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear320-hmi", "st,spear320";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 st,pinmux-mode = <4>;
24 pinctrl-names = "default";
25 pinctrl-0 = <&state_default>;
29 st,pins = "i2c0_grp";
33 st,pins = "ssp0_grp";
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622-rfb1.dts6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 chassis-type = "embedded";
19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
[all …]
H A Dmt7622-bananapi-bpi-r64.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
[all …]
/openbmc/linux/arch/arm/boot/dts/sunplus/
H A Dsunplus-sp7021.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/sunplus,sp7021-clkc.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/reset/sunplus,sp7021-reset.h>
11 #include <dt-bindings/pinctrl/sppctl-sp7021.h>
12 #include <dt-bindings/gpio/gpio.h>
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <XTAL>;
25 clock-output-names = "extclk";
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-foxg20.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-foxg20.dts - Device Tree file for Acme Systems FoxG20 board
9 /dts-v1/;
26 clock-frequency = <32768>;
30 clock-frequency = <18432000>;
38 compatible = "atmel,tcb-timer";
43 compatible = "atmel,tcb-timer";
49 atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>;
54 pinctrl-0 = <
58 pinctrl-names = "default";
[all …]
H A Dat91sam9260.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
7 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clock/at91.h>
14 #include <dt-bindings/mfd/at91-usart.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
[all …]
H A Dat91-sama5d3_xplained.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
14 compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5";
17 stdout-path = "serial0:115200n8";
26 clock-frequency = <32768>;
30 clock-frequency = <12000000>;
37 …pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd…
38 vmmc-supply = <&vcc_mmc0_reg>;
[all …]
H A Dat91-sama5d4_xplained.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
14 compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5";
17 stdout-path = "serial0:115200n8";
26 clock-frequency = <32768>;
30 clock-frequency = <12000000>;
36 uart0: serial@f8004000 {
37 atmel,use-dma-rx;
[all …]
H A Dat91rm9200.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/mfd/at91-usart.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
23 interrupt-parent = <&aic>;
[all …]
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629-rfb.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
20 stdout-path = "serial0:115200n8";
23 gpio-keys {
24 compatible = "gpio-keys";
26 button-reset {
32 button-wps {
44 reg_3p3v: regulator-3p3v {
[all …]
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dnuvoton,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim LIU <JJLIU0@nuvoton.com>
14 information is in the NPCM7XX/8XX SERIAL I/O EXPANSION INTERFACE section.
15 Nuvoton NPCM7xx SGPIO module is combines a serial to parallel IC (HC595)
16 and a parallel to serial IC (HC165).
18 This interface has 4 pins (D_out , D_in, S_CLK, LDSH).
20 to 64 output pins, and up to 64 input pins, the pin is only for GPI or GPO.
21 GPIO pins can be programmed to support the following options
[all …]
/openbmc/linux/arch/mips/boot/dts/mscc/
H A Dserval.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
28 cpuintc: interrupt-controller {
29 #address-cells = <0>;
30 #interrupt-cells = <1>;
31 interrupt-controller;
32 compatible = "mti,cpu-interrupt-controller";
[all …]
H A Djaguar2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
29 cpuintc: interrupt-controller {
30 #address-cells = <0>;
31 #interrupt-cells = <1>;
32 interrupt-controller;
33 compatible = "mti,cpu-interrupt-controller";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-r40.dtsi2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-r40-ccu.h>
46 #include <dt-bindings/reset/sun8i-r40-ccu.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
51 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
[all …]
H A Darmada-xp-synology-ds414.dts13 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
16 * were delivered with an older version of u-boot that left internal
21 * installing it from u-boot prompt) or adjust the Devive Tree
25 /dts-v1/;
27 #include <dt-bindings/input/input.h>
28 #include <dt-bindings/gpio/gpio.h>
29 #include "armada-xp-mv78230.dtsi"
33 compatible = "synology,ds414", "marvell,armadaxp-mv78230",
34 "marvell,armadaxp", "marvell,armada-370-xp";
38 stdout-path = &uart0;
[all …]
H A Dat91-sama5d3_xplained.dts2 * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board
9 /dts-v1/;
14 compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5";
17 u-boot,dm-pre-reloc;
18 stdout-path = &dbgu;
31 clock-frequency = <32768>;
35 clock-frequency = <12000000>;
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_onewire_tm_default>;
54 u-boot,dm-pre-reloc;
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq4019-ap.dk04.1.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
17 stdout-path = "serial0:115200n8";
27 serial_0_pins: serial0-pinmux {
28 pins = "gpio16", "gpio17";
30 bias-disable;
33 serial_1_pins: serial1-pinmux {
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-synology-ds414.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-xp-mv78230.dtsi"
29 compatible = "synology,ds414", "marvell,armadaxp-mv78230",
30 "marvell,armadaxp", "marvell,armada-370-xp";
[all …]
H A Dkirkwood-openblocks_a6.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6282.dtsi"
9 compatible = "plathome,openblocks-a6", "marvell,kirkwood-88f6283", "marvell,kirkwood";
18 stdout-path = &uart0;
22 serial@12000 {
26 serial@12100 {
31 nr-ports = <1>;
44 pinctrl: pin-controller@10000 {
45 pinctrl-0 = <&pmx_dip_switches>;
[all …]
H A Darmada-370-synology-ds213j.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-370.dtsi"
30 "marvell,armada-370-xp";
33 stdout-path = "serial0:115200n8";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dstih407-c8sectpfe.txt5 stream data into the SoC on the TS pins, and into DDR for further processing.
9 located on an external DVB frontend card connected to SoC TS input pins.
14 - compatible : Should be "stih407-c8sectpfe"
16 - reg : Address and length of register sets for each device in
17 "reg-names"
19 - reg-names : The names of the register addresses corresponding to the
21 - c8sectpfe: c8sectpfe registers
22 - c8sectpfe-ram: c8sectpfe internal sram
24 - clocks : phandle list of c8sectpfe clocks
25 - clock-names : should be "c8sectpfe"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dpl011.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/pl011.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM AMBA Primecell PL011 serial UART
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/arm/primecell.yaml#
14 - $ref: serial.yaml#
22 - arm,pl011
24 - compatible
[all …]

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