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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Xenon SDHCI Controller
11 mmc-controller.yaml and the properties used by the Xenon implementation.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
[all …]
H A Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
[all …]
H A Dsdhci-st.txt1 * STMicroelectronics sdhci-st MMC/SD controller
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
13 - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14 See: Documentation/devicetree/bindings/resource-names.txt
15 - clocks: Phandle to the clock.
16 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - interrupts: One mmc interrupt should be described here.
19 - interrupt-names: Should be "mmcirq".
21 - pinctrl-names: A pinctrl state names "default" must be defined.
[all …]
H A Dbrcm,iproc-sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/brcm,iproc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom IPROC SDHCI controller
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
12 - Nicolas Saenz Julienne <nsaenz@kernel.org>
15 - $ref: mmc-controller.yaml#
20 - brcm,bcm2835-sdhci
[all …]
H A Dnvidia,tegra20-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 mmc-controller.yaml and the properties for the Tegra SDHCI controller.
23 - enum:
24 - nvidia,tegra20-sdhci
25 - nvidia,tegra30-sdhci
[all …]
H A Dsdhci-msm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
13 Secure Digital Host Controller Interface (SDHCI) present on
19 - enum:
20 - qcom,sdhci-msm-v4
22 - items:
[all …]
H A Daspeed,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later
4 ---
5 $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Ryan Chen <ryanchen.aspeed@gmail.com>
16 Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if
26 - aspeed,ast2400-sd-controller
27 - aspeed,ast2500-sd-controller
28 - aspeed,ast2600-sd-controller
[all …]
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arasan SDHCI Controller
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
[all …]
H A Dsdhci-pxa.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell PXA SDHCI v1/v2/v3
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: marvell,armada-380-sdhci
23 reg-names:
[all …]
H A Dsdhci-sprd.txt1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
17 "2x_enable" - gate clock controlling the device for some special platforms (optional)
[all …]
H A Dmicrochip,dw-sparx5-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: mmc-controller.yaml
13 - Lars Povlsen <lars.povlsen@microchip.com>
18 const: microchip,dw-sparx5-sdhci
29 Handle to "core" clock for the sdhci controller.
31 clock-names:
33 - const: core
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-of-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include "sdhci-pltfm.h"
28 #define ASPEED_SDC_S1_PHASE_OUT_EN GENMASK(9, 8)
85 * -----|-------------|----------|------------
108 writel(cap_val, sdc->regs + mirror_reg_offset); in aspeed_sdc_set_slot_capability()
112 struct aspeed_sdhci *sdhci, in aspeed_sdc_configure_8bit_mode() argument
117 /* Set/clear 8 bit mode */ in aspeed_sdc_configure_8bit_mode()
118 spin_lock(&sdc->lock); in aspeed_sdc_configure_8bit_mode()
119 info = readl(sdc->regs + ASPEED_SDC_INFO); in aspeed_sdc_configure_8bit_mode()
121 info |= sdhci->width_mask; in aspeed_sdc_configure_8bit_mode()
[all …]
H A Dsdhci-s3c.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
9 * SDHCI (HSMMC) support for Samsung SoC
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
29 #include "sdhci.h"
63 #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
86 #define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
87 #define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
88 #define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
[all …]
H A Dsdhci-st.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for SDHCI on STMicroelectronics SoCs
9 * Based on sdhci-cns3xxx.c
18 #include "sdhci-pltfm.h"
31 #define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT BIT(8)
59 #define ST_MMC_CCONFIG_3P3_VOLT BIT(8)
72 #define ST_MMC_CCONFIG_DDR50 BIT(8)
78 #define ST_MMC_CCONFIG_TUNING_FOR_SDR50 BIT(8)
88 #define ST_TOP_MMC_DLY_FIX_OFF(x) (x - 0x8)
97 #define ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE BIT(8)
[all …]
H A Dsdhci-pltfm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sdhci-pltfm.c Support for SDHCI platform devices
14 * SDHCI platform devices
16 * Inspired by sdhci-pci.c, by Pierre Ossman
26 #include "sdhci-pltfm.h"
32 return clk_get_rate(pltfm_host->clk); in sdhci_pltfm_clk_get_max_clock()
45 if (device_property_present(dev, "sdhci,wp-inverted") || in sdhci_wp_inverted()
46 device_property_present(dev, "wp-inverted")) in sdhci_wp_inverted()
49 /* Old device trees don't have the wp-inverted property. */ in sdhci_wp_inverted()
60 struct device_node *np = pdev->dev.of_node; in sdhci_get_compatibility()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmvebu-gated-clock.txt12 -----------------------------------
21 17 sdio SDHCI Host
29 -----------------------------------
35 8 audio Audio Cntrl
40 17 sdio SDHCI Host
56 -----------------------------------
64 8 pex0 PCIe 0
83 -----------------------------------
87 8 pex0 PCIe 0
97 -----------------------------------
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra30-tamonten.dtsi5 compatible = "ad,tamonten-ng", "nvidia,tegra30";
12 stdout-path = &uartd;
21 mmc0 = "/sdhci@78000600";
22 mmc1 = "/sdhci@78000400";
23 mmc2 = "/sdhci@78000000";
30 clock-frequency = <100000>;
35 clock-frequency = <100000>;
41 clock-frequency = <100000>;
47 clock-frequency = <100000>;
53 clock-frequency = <100000>;
[all …]
H A Dtegra210-p2371-0000.dts1 /dts-v1/;
6 model = "NVIDIA P2371-0000";
7 compatible = "nvidia,p2371-0000", "nvidia,tegra210";
10 stdout-path = &uarta;
15 mmc0 = "/sdhci@700b0600";
16 mmc1 = "/sdhci@700b0000";
24 sdhci@700b0000 {
26 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
27 power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
28 bus-width = <4>;
[all …]
H A Dtegra210-e2220-1170.dts1 /dts-v1/;
6 model = "NVIDIA E2220-1170";
7 compatible = "nvidia,e2220-1170", "nvidia,tegra210";
10 stdout-path = &uarta;
15 mmc0 = "/sdhci@700b0600";
16 mmc1 = "/sdhci@700b0000";
24 sdhci@700b0000 {
26 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
27 power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
28 bus-width = <4>;
[all …]
H A Dtegra186-p2771-0000.dtsi4 model = "NVIDIA P2771-0000";
5 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
8 stdout-path = &uarta;
12 mmc0 = "/sdhci@3460000";
13 mmc1 = "/sdhci@3400000";
30 phy-reset-gpios = <&gpio_main TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
49 sdhci@3400000 {
51 wp-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
52 bus-width = <4>;
55 sdhci@3460000 {
[all …]
H A Dtegra30-apalis.dts1 /dts-v1/;
10 stdout-path = &uarta;
18 mmc0 = "/sdhci@78000600";
19 mmc1 = "/sdhci@78000400";
20 mmc2 = "/sdhci@78000000";
35 pcie-controller@00003000 {
37 avdd-pexa-supply = <&vdd2_reg>;
38 vdd-pexa-supply = <&vdd2_reg>;
39 avdd-pexb-supply = <&vdd2_reg>;
40 vdd-pexb-supply = <&vdd2_reg>;
[all …]
H A Dtegra114-dalmore.dts1 /dts-v1/;
10 stdout-path = &uartd;
19 mmc0 = "/sdhci@78000600";
20 mmc1 = "/sdhci@78000400";
32 clock-frequency = <100000>;
37 clock-frequency = <100000>;
42 clock-frequency = <100000>;
47 clock-frequency = <100000>;
52 clock-frequency = <400000>;
57 spi-max-frequency = <25000000>;
[all …]
/openbmc/u-boot/drivers/mmc/
H A Dbcm2835_sdhci.c3 * git://github.com/gonzoua/u-boot-pi.git master
6 * Tweaks for U-Boot upstreaming
9 * Portions (e.g. read/write macros, concepts for back-to-back register write
11 * https://github.com/raspberrypi/linux.git rpi-3.6.y
16 * Support for SDHCI device on 2835
17 * Based on sdhci-bcm2708.c (c) 2010 Broadcom
34 * SDHCI platform device - Arasan SD controller in BCM2708
36 * Inspired by sdhci-pci.c, by Pierre Ossman
43 #include <sdhci.h>
46 #include <mach/sdhci.h>
[all …]
H A DKconfig31 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
32 and non-removable (e.g. eMMC chip) devices are supported. These
33 appear as block devices in U-Boot and can support filesystems such
42 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
43 and non-removable (e.g. eMMC chip) devices are supported. These
44 appear as block devices in U-Boot and can support filesystems such
161 you are reading this help text, you most likely have no idea :-)
213 as removeable SD and micro-SD cards.
256 This selects PCI-based MMC controllers.
285 This enables extended-drain in the MMC/SD/SDIO1I/O and
[all …]
/openbmc/qemu/tests/qtest/
H A Dnpcm7xx_sdhci-test.c2 * QTests for NPCM7xx SD-3.0 / MMC-4.51 Host Controller
21 #include "libqtest-single.h"
22 #include "libqos/sdhci-cmd.h"
36 "-machine kudo-bmc " in setup_sd_card()
37 "-device sd-card,drive=drive0 " in setup_sd_card()
38 "-drive id=drive0,if=none,file=%s,format=raw,auto-read-only=off", in setup_sd_card()
46 sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x41200000, 0, (41 << 8)); in setup_sd_card()
70 /* read message using sdhci */ in write_sdread()
95 /* write message using sdhci */ in sdwrite_read()
121 /* Check SDHCI has correct default values. */
[all …]

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