1ae5c0585SLubomir Rintel# SPDX-License-Identifier: GPL-2.0-only 2ae5c0585SLubomir Rintel%YAML 1.2 3ae5c0585SLubomir Rintel--- 4ae5c0585SLubomir Rintel$id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml# 5ae5c0585SLubomir Rintel$schema: http://devicetree.org/meta-schemas/core.yaml# 6ae5c0585SLubomir Rintel 7*c6ecb0f8SDoug Browntitle: Marvell PXA SDHCI v1/v2/v3 8ae5c0585SLubomir Rintel 9ae5c0585SLubomir Rintelmaintainers: 10ae5c0585SLubomir Rintel - Ulf Hansson <ulf.hansson@linaro.org> 11ae5c0585SLubomir Rintel 12ae5c0585SLubomir RintelallOf: 13ae5c0585SLubomir Rintel - $ref: mmc-controller.yaml# 14ae5c0585SLubomir Rintel - if: 15ae5c0585SLubomir Rintel properties: 16ae5c0585SLubomir Rintel compatible: 17ae5c0585SLubomir Rintel contains: 18ae5c0585SLubomir Rintel const: marvell,armada-380-sdhci 19ae5c0585SLubomir Rintel then: 20ae5c0585SLubomir Rintel properties: 21ae5c0585SLubomir Rintel regs: 22ae5c0585SLubomir Rintel minItems: 3 23ae5c0585SLubomir Rintel reg-names: 24ae5c0585SLubomir Rintel minItems: 3 25ae5c0585SLubomir Rintel required: 26ae5c0585SLubomir Rintel - reg-names 27ae5c0585SLubomir Rintel else: 28ae5c0585SLubomir Rintel properties: 29ae5c0585SLubomir Rintel regs: 30ae5c0585SLubomir Rintel maxItems: 1 31ae5c0585SLubomir Rintel reg-names: 32ae5c0585SLubomir Rintel maxItems: 1 33ae5c0585SLubomir Rintel 34ae5c0585SLubomir Rintelproperties: 35ae5c0585SLubomir Rintel compatible: 36ae5c0585SLubomir Rintel enum: 37*c6ecb0f8SDoug Brown - mrvl,pxav1-mmc 38ae5c0585SLubomir Rintel - mrvl,pxav2-mmc 39ae5c0585SLubomir Rintel - mrvl,pxav3-mmc 40ae5c0585SLubomir Rintel - marvell,armada-380-sdhci 41ae5c0585SLubomir Rintel 42ae5c0585SLubomir Rintel reg: 43ae5c0585SLubomir Rintel minItems: 1 44ae5c0585SLubomir Rintel maxItems: 3 45ae5c0585SLubomir Rintel 46ae5c0585SLubomir Rintel reg-names: 47ae5c0585SLubomir Rintel items: 48ae5c0585SLubomir Rintel - const: sdhci 49ae5c0585SLubomir Rintel - const: mbus 50ae5c0585SLubomir Rintel - const: conf-sdio3 51ae5c0585SLubomir Rintel 52ae5c0585SLubomir Rintel interrupts: 53ae5c0585SLubomir Rintel maxItems: 1 54ae5c0585SLubomir Rintel 55ae5c0585SLubomir Rintel clocks: 56ae5c0585SLubomir Rintel minItems: 1 57ae5c0585SLubomir Rintel maxItems: 2 58ae5c0585SLubomir Rintel 59ae5c0585SLubomir Rintel clock-names: 60ae5c0585SLubomir Rintel minItems: 1 61ae5c0585SLubomir Rintel items: 62ae5c0585SLubomir Rintel - const: io 63ae5c0585SLubomir Rintel - const: core 64ae5c0585SLubomir Rintel 65*c6ecb0f8SDoug Brown pinctrl-names: 66*c6ecb0f8SDoug Brown description: 67*c6ecb0f8SDoug Brown Optional for supporting PXA168 SDIO IRQ errata to switch CMD pin between 68*c6ecb0f8SDoug Brown SDIO CMD and GPIO mode. 69*c6ecb0f8SDoug Brown items: 70*c6ecb0f8SDoug Brown - const: default 71*c6ecb0f8SDoug Brown - const: state_cmd_gpio 72*c6ecb0f8SDoug Brown 73*c6ecb0f8SDoug Brown pinctrl-0: 74*c6ecb0f8SDoug Brown description: 75*c6ecb0f8SDoug Brown Should contain default pinctrl. 76*c6ecb0f8SDoug Brown 77*c6ecb0f8SDoug Brown pinctrl-1: 78*c6ecb0f8SDoug Brown description: 79*c6ecb0f8SDoug Brown Should switch CMD pin to GPIO mode as a high output. 80*c6ecb0f8SDoug Brown 81ae5c0585SLubomir Rintel mrvl,clk-delay-cycles: 82ae5c0585SLubomir Rintel description: Specify a number of cycles to delay for tuning. 83ae5c0585SLubomir Rintel $ref: /schemas/types.yaml#/definitions/uint32 84ae5c0585SLubomir Rintel 85ae5c0585SLubomir Rintelrequired: 86ae5c0585SLubomir Rintel - compatible 87ae5c0585SLubomir Rintel - reg 88ae5c0585SLubomir Rintel - interrupts 89ae5c0585SLubomir Rintel - clocks 90ae5c0585SLubomir Rintel - clock-names 91ae5c0585SLubomir Rintel 926fdc6e23SRob HerringunevaluatedProperties: false 936fdc6e23SRob Herring 94ae5c0585SLubomir Rintelexamples: 95ae5c0585SLubomir Rintel - | 96ae5c0585SLubomir Rintel #include <dt-bindings/clock/berlin2.h> 97ae5c0585SLubomir Rintel mmc@d4280800 { 98ae5c0585SLubomir Rintel compatible = "mrvl,pxav3-mmc"; 99ae5c0585SLubomir Rintel reg = <0xd4280800 0x800>; 100ae5c0585SLubomir Rintel bus-width = <8>; 101ae5c0585SLubomir Rintel interrupts = <27>; 102ae5c0585SLubomir Rintel clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; 103ae5c0585SLubomir Rintel clock-names = "io", "core"; 104ae5c0585SLubomir Rintel non-removable; 105ae5c0585SLubomir Rintel mrvl,clk-delay-cycles = <31>; 106ae5c0585SLubomir Rintel }; 107ae5c0585SLubomir Rintel - | 108ae5c0585SLubomir Rintel mmc@d8000 { 109ae5c0585SLubomir Rintel compatible = "marvell,armada-380-sdhci"; 110ae5c0585SLubomir Rintel reg-names = "sdhci", "mbus", "conf-sdio3"; 111ae5c0585SLubomir Rintel reg = <0xd8000 0x1000>, 112ae5c0585SLubomir Rintel <0xdc000 0x100>, 113ae5c0585SLubomir Rintel <0x18454 0x4>; 114ae5c0585SLubomir Rintel interrupts = <0 25 0x4>; 115ae5c0585SLubomir Rintel clocks = <&gateclk 17>; 116ae5c0585SLubomir Rintel clock-names = "io"; 117ae5c0585SLubomir Rintel mrvl,clk-delay-cycles = <0x1F>; 118ae5c0585SLubomir Rintel }; 119ae5c0585SLubomir Rintel 120ae5c0585SLubomir Rintel... 121