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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmvebu-gated-clock.txt12 -----------------------------------
18 5 pex0 PCIe Cntrl 0
21 17 sdio SDHCI Host
29 -----------------------------------
33 5 pex0 PCIe 0 Clock out
40 17 sdio SDHCI Host
56 -----------------------------------
61 5 pex1 PCIe 1
83 -----------------------------------
84 5 pex1 PCIe 1
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-of-hlwd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/mmc/host/sdhci-of-hlwd.c
9 * Based on sdhci-of-esdhc.c
21 #include "sdhci-pltfm.h"
24 * Ops and quirks for the Nintendo Wii SDHCI controllers.
30 #define SDHCI_HLWD_WRITE_DELAY 5 /* usecs */
75 { .compatible = "nintendo,hollywood-sdhci" },
82 .name = "sdhci-hlwd",
93 MODULE_DESCRIPTION("Nintendo Wii SDHCI OF driver");
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsamsung,s3c6410-sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,s3c6410-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC SDHCI Controller
10 - Jaehoon Chung <jh80.chung@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
16 - samsung,s3c6410-sdhci
17 - samsung,exynos4210-sdhci
24 maxItems: 5
[all …]
H A Dsnps,dwcmshc-sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
14 - $ref: mmc-controller.yaml#
19 - rockchip,rk3568-dwcmshc
20 - rockchip,rk3588-dwcmshc
21 - snps,dwcmshc-sdhci
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra30-tamonten.dtsi5 compatible = "ad,tamonten-ng", "nvidia,tegra30";
12 stdout-path = &uartd;
21 mmc0 = "/sdhci@78000600";
22 mmc1 = "/sdhci@78000400";
23 mmc2 = "/sdhci@78000000";
30 clock-frequency = <100000>;
35 clock-frequency = <100000>;
41 clock-frequency = <100000>;
47 clock-frequency = <100000>;
53 clock-frequency = <100000>;
[all …]
H A Dexynos4.dtsi1 // SPDX-License-Identifier: GPL-2.0+
23 combiner: interrupt-controller@10440000 {
24 compatible = "samsung,exynos4210-combiner";
25 #interrupt-cells = <2>;
26 interrupt-controller;
30 gic: interrupt-controller@10490000 {
31 compatible = "arm,cortex-a9-gic";
32 #interrupt-cells = <3>;
33 interrupt-controller;
34 cpu-offset = <0x4000>;
[all …]
H A Dtegra210-p2371-2180.dts1 /dts-v1/;
6 model = "NVIDIA P2371-2180";
7 compatible = "nvidia,p2371-2180", "nvidia,tegra210";
10 stdout-path = &uarta;
15 mmc0 = "/sdhci@700b0600";
16 mmc1 = "/sdhci@700b0000";
24 pcie-controller@01003000 {
37 pinctrl-0 = <&padctl_default>;
38 pinctrl-names = "default";
42 nvidia,lanes = "otg-1", "otg-2";
[all …]
H A Dtegra124-venice2.dts1 /dts-v1/;
10 stdout-path = &uarta;
20 mmc0 = "/sdhci@700b0600";
21 mmc1 = "/sdhci@700b0400";
35 clock-frequency = <100000>;
40 clock-frequency = <100000>;
45 clock-frequency = <100000>;
50 clock-frequency = <100000>;
55 clock-frequency = <400000>;
60 clock-frequency = <400000>;
[all …]
H A Dtegra30-apalis.dts1 /dts-v1/;
10 stdout-path = &uarta;
18 mmc0 = "/sdhci@78000600";
19 mmc1 = "/sdhci@78000400";
20 mmc2 = "/sdhci@78000000";
35 pcie-controller@00003000 {
37 avdd-pexa-supply = <&vdd2_reg>;
38 vdd-pexa-supply = <&vdd2_reg>;
39 avdd-pexb-supply = <&vdd2_reg>;
40 vdd-pexb-supply = <&vdd2_reg>;
[all …]
H A Dtegra30.dtsi1 #include <dt-bindings/clock/tegra30-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra30-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&lic>;
13 pcie-controller@00003000 {
14 compatible = "nvidia,tegra30-pcie";
19 reg-names = "pads", "afi", "cs";
22 interrupt-names = "intr", "msi";
[all …]
H A Dtegra114.dtsi1 #include <dt-bindings/clock/tegra114-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra114-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&lic>;
14 compatible = "nvidia,tegra114-host1x", "simple-bus";
20 reset-names = "host1x";
22 #address-cells = <1>;
23 #size-cells = <1>;
[all …]
H A Dtegra210.dtsi1 #include <dt-bindings/clock/tegra210-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra210-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
10 interrupt-parent = <&lic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 pcie-controller@01003000 {
[all …]
H A Dtegra30-beaver.dts1 /dts-v1/;
10 stdout-path = &uarta;
19 mmc0 = "/sdhci@78000600";
20 mmc1 = "/sdhci@78000000";
31 pcie-controller@00003000 {
34 avdd-pexa-supply = <&ldo1_reg>;
35 vdd-pexa-supply = <&ldo1_reg>;
36 avdd-pexb-supply = <&ldo1_reg>;
37 vdd-pexb-supply = <&ldo1_reg>;
38 avdd-pex-pll-supply = <&ldo1_reg>;
[all …]
/openbmc/u-boot/drivers/mmc/
H A DKconfig31 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
32 and non-removable (e.g. eMMC chip) devices are supported. These
33 appear as block devices in U-Boot and can support filesystems such
42 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
43 and non-removable (e.g. eMMC chip) devices are supported. These
44 appear as block devices in U-Boot and can support filesystems such
161 you are reading this help text, you most likely have no idea :-)
213 as removeable SD and micro-SD cards.
256 This selects PCI-based MMC controllers.
285 This enables extended-drain in the MMC/SD/SDIO1I/O and
[all …]
H A Dtegra_mmc.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Portions Copyright 2011-2016 NVIDIA Corporation
16 #include <asm/arch-tegra/tegra_mmc.h>
30 unsigned int version; /* SDHCI spec. version */
40 if (power != (unsigned short)-1) { in tegra_mmc_set_power()
58 writeb(pwr, &priv->reg->pwrcon); in tegra_mmc_set_power()
64 writeb(pwr, &priv->reg->pwrcon); in tegra_mmc_set_power()
74 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n", in tegra_mmc_prepare_data()
75 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks, in tegra_mmc_prepare_data()
76 data->blocksize); in tegra_mmc_prepare_data()
[all …]
/openbmc/u-boot/include/
H A Dsdhci.h1 /* SPDX-License-Identifier: GPL-2.0+ */
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
34 #define SDHCI_TRNS_MULTI BIT(5)
76 #define SDHCI_CTRL_8BITBUS BIT(5)
99 #define SDHCI_PROG_CLOCK_MODE BIT(5)
118 #define SDHCI_INT_DATA_AVAIL BIT(5)
143 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
183 /* 4C-4F reserved for more max current */
190 /* 55-57 reserved */
194 /* 60-FB reserved */
[all …]
/openbmc/linux/drivers/clk/samsung/
H A Dclk-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
17 #include "clk-pll.h"
98 /* S3C6400-specific parent clocks. */
103 /* S3C6410-specific parent clocks. */
142 MUX(MOUT_UHOST, "mout_uhost", uhost_p6400, CLK_SRC, 5, 2),
150 MUX(MOUT_UHOST, "mout_uhost", uhost_p6410, CLK_SRC, 5, 2),
216 GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5),
240 GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5),
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm6115p-lenovo-j606f.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
14 chassis-type = "tablet";
17 qcom,msm-id = <445 0x10000>, <420 0x10000>;
18 qcom,board-id = <34 3>;
25 #address-cells = <2>;
26 #size-cells = <2>;
29 framebuffer0: framebuffer@5c000000 {
30 compatible = "simple-framebuffer";
40 gpio-keys {
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dwii.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2008-2009 The GameCube Linux Team
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
15 * This is commented-out for now.
25 #address-cells = <1>;
26 #size-cells = <1>;
29 bootargs = "root=/dev/mmcblk0p2 rootwait udbg-immortal";
34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
[all …]
/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7621.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "pinctrl-mtmips.h"
14 #define MT7621_GPIO_MODE_UART2_SHIFT 5
40 FUNC("uart3", 0, 5, 4),
41 FUNC("i2s", 2, 5, 4),
42 FUNC("spdif3", 3, 5, 4),
49 static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
65 FUNC("sdhci", 0, 41, 8),
87 GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
99 { .compatible = "ralink,mt7621-pinctrl" },
[all …]
/openbmc/linux/include/linux/platform_data/
H A Dpxa_sdhci.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * PXA Platform - SDHCI platform data definitions
17 /* card always wired to host, like on-chip emmc */
19 /* Board design supports 8-bit data on SD/SDIO BUS */
23 * struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI
26 * mmp2: each step is roughly 100ps, 5bits width
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl_spear.txt4 - compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
9 - reg : Address range of the pinctrl registers
10 - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
11 - Its values for SPEAr300:
12 - NAND_MODE : <0>
13 - NOR_MODE : <1>
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
22 maxItems: 5
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
/openbmc/linux/drivers/phy/intel/
H A Dphy-intel-keembay-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #define DLL_RDY_MASK BIT(5)
66 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
69 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in keembay_emmc_phy_power()
73 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK, in keembay_emmc_phy_power()
76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
100 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
107 udelay(5); in keembay_emmc_phy_power()
109 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
[all …]

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