| /openbmc/u-boot/drivers/ata/ |
| H A D | Kconfig | 2 bool "Support SATA controllers with driver model"
5 This enables a uclass for disk controllers in U-Boot. Various driver
6 types can use this, such as AHCI/SATA. It does not provide any standard
10 config SATA config
11 bool "Support SATA controllers"
14 This enables support for SATA (Serial Advanced Technology
18 SATA replaces PATA (originally just ATA), which stands for Parallel AT
22 See also CMD_SATA which provides command-line support.
30 bool "Enable SCSI interface to SATA devices"
33 Enable this to allow interfacing SATA devices via the SCSI layer.
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| H A D | fsl_sata.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007-2008 Freescale Semiconductor, Inc.
10 #define SATA_HC_MAX_NUM 4 /* Max host controller numbers */
11 #define SATA_HC_MAX_CMD 16 /* Max command queue depth per host controller */
12 #define SATA_HC_MAX_PORT 16 /* Max port number per host controller */
15 * SATA Host Controller Registers
18 /* SATA command registers */
36 /* SATA supperset registers */
37 u32 sstatus; /* SATA interface status register */
38 u32 serror; /* SATA interface error register */
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| /openbmc/linux/drivers/ata/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # SATA/PATA driver configuration
10 uses pata-platform driver to enable the relevant driver in the
21 If you want to use an ATA hard disk, ATA tape drive, ATA CD-ROM or
24 that "speaks" the ATA protocol, also called ATA controller),
62 <file:Documentation/admin-guide/kernel-parameters.txt>.
76 This option adds support for ATA-related ACPI objects.
78 from the ACPI BIOS and write them to the disk controller.
85 bool "SATA Zero Power Optical Disc Drive (ZPODD) support"
88 This option adds support for SATA Zero Power Optical Disc
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| H A D | ata_piix.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ata_piix.c - Intel PATA/SATA controllers
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
14 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
15 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
19 * as Documentation/driver-api/libata.rst
32 * change little except in gaining more modes until SATA arrives. This
40 * PIIX4 errata #9 - Only on ultra obscure hw
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| /openbmc/linux/Documentation/devicetree/bindings/ata/ |
| H A D | fsl-sata.txt | 1 * Freescale 8xxx/3.0 Gb/s SATA nodes
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA port should have its own node.
7 - compatible : compatible list, contains 2 entries, first is
8 "fsl,CHIP-sata", where CHIP is the processor
10 "fsl,pq-sata"
11 - interrupts : <interrupt mapping for SATA IRQ>
12 - cell-index : controller index.
13 1 for controller @ 0x18000
14 2 for controller @ 0x19000
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| H A D | apm-xgene.txt | 1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
4 controllers. Each SATA controller (pair of ports) have its own node.
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
11 Second memory resource shall be the host controller
13 Third memory resource shall be the host controller
15 4th memory resource shall be the host controller
18 controller MUX memory resource if required.
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| H A D | ahci-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
14 This document defines device tree properties for a common AHCI SATA
15 controller implementation. It's hardware interface is supposed to
17 Advanced Host Controller Interface specification for details). The
18 document doesn't constitute a DT-node binding by itself but merely
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| H A D | sata-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/sata-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Serial AT attachment (SATA) controllers
10 - Linus Walleij <linus.walleij@linaro.org>
14 AT attachment (SATA) storage devices. It doesn't constitute a device tree
18 The SATA controller-specific device tree bindings are responsible for
23 pattern: "^sata(@.*)?$"
25 Specifies the host controller node. SATA host controller nodes are named
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| H A D | faraday,ftide010.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Faraday Technology FTIDE010 PATA controller
10 - Linus Walleij <linus.walleij@linaro.org>
13 This controller is the first Faraday IDE interface block, used in the
15 platform. The controller can do PIO modes 0 through 4, Multi-word DMA
19 SATA bridge in order to support SATA. This is why a phandle to that
20 controller is compulsory on that platform.
22 The timing properties are unique per-SoC, not per-board.
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| H A D | imx-sata.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX AHCI SATA Controller
10 - Shawn Guo <shawn.guo@linaro.org>
13 The Freescale i.MX SATA controller mostly conforms to the AHCI interface
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
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| H A D | snps,dwc-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller.
20 - snps,dwc-ahci
21 - snps,spear-ahci
23 - compatible
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| H A D | ahci-platform.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AHCI SATA Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
11 Each SATA controller should have its own node.
13 It is possible, but not required, to represent each port as a sub-node.
18 - Hans de Goede <hdegoede@redhat.com>
19 - Jens Axboe <axboe@kernel.dk>
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| H A D | rockchip,dwc-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller found in Rockchip
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
25 - compatible
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| H A D | marvell.txt | 1 * Marvell Orion SATA
4 - compatibility : "marvell,orion-sata" or "marvell,armada-370-sata"
5 - reg : Address range of controller
6 - interrupts : Interrupt controller is using
7 - nr-ports : Number of SATA ports in use.
10 - phys : List of phandles to sata phys
11 - phy-names : Should be "0", "1", etc, one number per phandle
15 sata@80000 {
16 compatible = "marvell,orion-sata";
20 phy-names = "0", "1";
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| H A D | nvidia,tegra-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra AHCI SATA Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra124-ahci
17 - nvidia,tegra132-ahci
18 - nvidia,tegra210-ahci
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| H A D | qcom-sata.txt | 1 * Qualcomm AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA controller should have its own node.
7 - compatible : compatible list, must contain "generic-ahci"
8 - interrupts : <interrupt mapping for SATA IRQ>
9 - reg : <registers mapping>
10 - phys : Must contain exactly one entry as specified
11 in phy-bindings.txt
12 - phy-names : Must be "sata-phy"
14 Required properties for "qcom,ipq806x-ahci" compatible:
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| H A D | cortina,gemini-sata-bridge.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cortina Systems Gemini SATA Bridge
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
15 them in different configurations to two SATA ports.
19 const: cortina,gemini-sata-bridge
26 description: phandles to the reset lines for both SATA bridges
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-miphy365x.txt | 5 for SATA and PCIe.
7 Required properties (controller (parent) node):
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
17 nodes to describe the controller's topology. These nodes
21 - #phy-cells : Should be 1 (See second example)
23 - PHY_TYPE_SATA
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| H A D | qcom-ipq806x-sata-phy.txt | 1 Qualcomm IPQ806x SATA PHY Controller
2 ------------------------------------
4 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
5 Each SATA PHY controller should have its own node.
8 - compatible: compatible list, contains "qcom,ipq806x-sata-phy"
9 - reg: offset and length of the SATA PHY register set;
10 - #phy-cells: must be zero
11 - clocks: must be exactly one entry
12 - clock-names: must be "cfg"
15 sata_phy: sata-phy@1b400000 {
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| H A D | qcom-apq8064-sata-phy.txt | 1 Qualcomm APQ8064 SATA PHY Controller
2 ------------------------------------
4 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
5 Each SATA PHY controller should have its own node.
8 - compatible: compatible list, contains "qcom,apq8064-sata-phy".
9 - reg: offset and length of the SATA PHY register set;
10 - #phy-cells: must be zero
11 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
12 clock-names.
13 - clock-names: must be "cfg" for phy config clock.
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| H A D | phy-mvebu.txt | 1 * Marvell MVEBU SATA PHY
3 Power control for the SATA phy found on Marvell MVEBU SoCs.
5 This document extends the binding described in phy-bindings.txt
9 - reg : Offset and length of the register set for the SATA device
10 - compatible : Should be "marvell,mvebu-sata-phy"
11 - clocks : phandle of clock and specifier that supplies the device
12 - clock-names : Should be "sata"
15 sata-phy@84000 {
16 compatible = "marvell,mvebu-sata-phy";
19 clock-names = "sata";
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| H A D | phy-miphy28lp.txt | 5 for SATA, PCIe or USB3.
7 Required properties (controller (parent) node):
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
10 which contain the SATA, PCIe or USB3 mode setting bits.
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
15 nodes to describe the controller's topology. These nodes
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
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| /openbmc/u-boot/include/ |
| H A D | ahci.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
30 /* Global controller registers */
39 #define HOST_RESET (1 << 0) /* reset controller; self-clear */
43 /* Registers for each SATA port */
54 #define PORT_SCR 0x28 /* SATA phy register block */
55 #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
56 #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
57 #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
58 #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
70 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
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| /openbmc/linux/drivers/phy/samsung/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver"
21 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
30 This driver provides PHY interface for Exynos PCIe controller.
39 controller to do PHY related programming.
77 are available - device and host.
89 This driver provides PHY interface for USB 3.0 DRD controller
93 tristate "Exynos5250 Sata SerDes/PHY driver"
102 Enable this to support SATA SerDes/Phy found on Samsung's
103 Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
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| /openbmc/u-boot/arch/x86/cpu/ivybridge/ |
| H A D | sata.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2008-2009 coresystems GmbH
33 /* SATA Initialization register */ in common_sata_init()
41 const void *blob = gd->fdt_blob; in bd82x6x_sata_init()
47 debug("SATA: Initializing...\n"); in bd82x6x_sata_init()
49 /* SATA configuration */ in bd82x6x_sata_init()
50 port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); in bd82x6x_sata_init()
54 mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); in bd82x6x_sata_init()
58 debug("SATA: Controller in AHCI mode\n"); in bd82x6x_sata_init()
73 /* Initialize AHCI memory-mapped space */ in bd82x6x_sata_init()
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