1*5d16dcd2SCorentin Labbe# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*5d16dcd2SCorentin Labbe%YAML 1.2
3*5d16dcd2SCorentin Labbe---
4*5d16dcd2SCorentin Labbe$id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
5*5d16dcd2SCorentin Labbe$schema: http://devicetree.org/meta-schemas/core.yaml#
6*5d16dcd2SCorentin Labbe
7*5d16dcd2SCorentin Labbetitle: Cortina Systems Gemini SATA Bridge
8*5d16dcd2SCorentin Labbe
9*5d16dcd2SCorentin Labbemaintainers:
10*5d16dcd2SCorentin Labbe  - Linus Walleij <linus.walleij@linaro.org>
11*5d16dcd2SCorentin Labbe
12*5d16dcd2SCorentin Labbedescription: |
13*5d16dcd2SCorentin Labbe    The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
14*5d16dcd2SCorentin Labbe    takes two Faraday Technology FTIDE010 PATA controllers and bridges
15*5d16dcd2SCorentin Labbe    them in different configurations to two SATA ports.
16*5d16dcd2SCorentin Labbe
17*5d16dcd2SCorentin Labbeproperties:
18*5d16dcd2SCorentin Labbe  compatible:
19*5d16dcd2SCorentin Labbe    const: cortina,gemini-sata-bridge
20*5d16dcd2SCorentin Labbe
21*5d16dcd2SCorentin Labbe  reg:
22*5d16dcd2SCorentin Labbe    maxItems: 1
23*5d16dcd2SCorentin Labbe
24*5d16dcd2SCorentin Labbe  resets:
25*5d16dcd2SCorentin Labbe    maxItems: 2
26*5d16dcd2SCorentin Labbe    description: phandles to the reset lines for both SATA bridges
27*5d16dcd2SCorentin Labbe
28*5d16dcd2SCorentin Labbe  reset-names:
29*5d16dcd2SCorentin Labbe    items:
30*5d16dcd2SCorentin Labbe      - const: sata0
31*5d16dcd2SCorentin Labbe      - const: sata1
32*5d16dcd2SCorentin Labbe
33*5d16dcd2SCorentin Labbe  clocks:
34*5d16dcd2SCorentin Labbe    maxItems: 2
35*5d16dcd2SCorentin Labbe    description: phandles to the compulsory peripheral clocks
36*5d16dcd2SCorentin Labbe
37*5d16dcd2SCorentin Labbe  clock-names:
38*5d16dcd2SCorentin Labbe    items:
39*5d16dcd2SCorentin Labbe      - const: SATA0_PCLK
40*5d16dcd2SCorentin Labbe      - const: SATA1_PCLK
41*5d16dcd2SCorentin Labbe
42*5d16dcd2SCorentin Labbe  syscon:
43*5d16dcd2SCorentin Labbe    $ref: /schemas/types.yaml#/definitions/phandle
44*5d16dcd2SCorentin Labbe    description: a phandle to the global Gemini system controller
45*5d16dcd2SCorentin Labbe
46*5d16dcd2SCorentin Labbe  cortina,gemini-ata-muxmode:
47*5d16dcd2SCorentin Labbe    $ref: /schemas/types.yaml#/definitions/uint32
48*5d16dcd2SCorentin Labbe    enum:
49*5d16dcd2SCorentin Labbe      - 0
50*5d16dcd2SCorentin Labbe      - 1
51*5d16dcd2SCorentin Labbe      - 2
52*5d16dcd2SCorentin Labbe      - 3
53*5d16dcd2SCorentin Labbe    description: |
54*5d16dcd2SCorentin Labbe      Tell the desired multiplexing mode for the ATA controller and SATA
55*5d16dcd2SCorentin Labbe      bridges.
56*5d16dcd2SCorentin Labbe      Mode 0: ata0 master <-> sata0
57*5d16dcd2SCorentin Labbe              ata1 master <-> sata1
58*5d16dcd2SCorentin Labbe              ata0 slave interface brought out on IDE pads
59*5d16dcd2SCorentin Labbe      Mode 1: ata0 master <-> sata0
60*5d16dcd2SCorentin Labbe              ata1 master <-> sata1
61*5d16dcd2SCorentin Labbe              ata1 slave interface brought out on IDE pads
62*5d16dcd2SCorentin Labbe      Mode 2: ata1 master <-> sata1
63*5d16dcd2SCorentin Labbe              ata1 slave  <-> sata0
64*5d16dcd2SCorentin Labbe              ata0 master and slave interfaces brought out on IDE pads
65*5d16dcd2SCorentin Labbe      Mode 3: ata0 master <-> sata0
66*5d16dcd2SCorentin Labbe              ata0 slave  <-> sata1
67*5d16dcd2SCorentin Labbe              ata1 master and slave interfaces brought out on IDE pads
68*5d16dcd2SCorentin Labbe
69*5d16dcd2SCorentin Labbe  cortina,gemini-enable-ide-pins:
70*5d16dcd2SCorentin Labbe    type: boolean
71*5d16dcd2SCorentin Labbe    description: Enables the PATA to IDE connection.
72*5d16dcd2SCorentin Labbe      The muxmode setting decides whether ATA0 or ATA1 is brought out,
73*5d16dcd2SCorentin Labbe      and whether master, slave or both interfaces get brought out.
74*5d16dcd2SCorentin Labbe
75*5d16dcd2SCorentin Labbe  cortina,gemini-enable-sata-bridge:
76*5d16dcd2SCorentin Labbe    type: boolean
77*5d16dcd2SCorentin Labbe    description: Enables the PATA to SATA bridge inside the Gemnini SoC.
78*5d16dcd2SCorentin Labbe      The Muxmode decides what PATA blocks will be muxed out and how.
79*5d16dcd2SCorentin Labbe
80*5d16dcd2SCorentin Labberequired:
81*5d16dcd2SCorentin Labbe  - clocks
82*5d16dcd2SCorentin Labbe  - clock-names
83*5d16dcd2SCorentin Labbe  - cortina,gemini-ata-muxmode
84*5d16dcd2SCorentin Labbe  - resets
85*5d16dcd2SCorentin Labbe  - reset-names
86*5d16dcd2SCorentin Labbe  - compatible
87*5d16dcd2SCorentin Labbe  - reg
88*5d16dcd2SCorentin Labbe  - syscon
89*5d16dcd2SCorentin Labbe
90*5d16dcd2SCorentin LabbeadditionalProperties: false
91*5d16dcd2SCorentin Labbe
92*5d16dcd2SCorentin Labbeexamples:
93*5d16dcd2SCorentin Labbe  - |
94*5d16dcd2SCorentin Labbe    #include <dt-bindings/clock/cortina,gemini-clock.h>
95*5d16dcd2SCorentin Labbe    sata@46000000 {
96*5d16dcd2SCorentin Labbe      compatible = "cortina,gemini-sata-bridge";
97*5d16dcd2SCorentin Labbe      reg = <0x46000000 0x100>;
98*5d16dcd2SCorentin Labbe      resets = <&rcon 26>, <&rcon 27>;
99*5d16dcd2SCorentin Labbe      reset-names = "sata0", "sata1";
100*5d16dcd2SCorentin Labbe      clocks = <&gcc GEMINI_CLK_GATE_SATA0>,
101*5d16dcd2SCorentin Labbe               <&gcc GEMINI_CLK_GATE_SATA1>;
102*5d16dcd2SCorentin Labbe      clock-names = "SATA0_PCLK", "SATA1_PCLK";
103*5d16dcd2SCorentin Labbe      syscon = <&syscon>;
104*5d16dcd2SCorentin Labbe      cortina,gemini-ata-muxmode = <3>;
105*5d16dcd2SCorentin Labbe      cortina,gemini-enable-ide-pins;
106*5d16dcd2SCorentin Labbe      cortina,gemini-enable-sata-bridge;
107*5d16dcd2SCorentin Labbe    };
108