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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
20 local-mac-address:
23 $ref: /schemas/types.yaml#/definitions/uint8-array
27 mac-address:
32 local-mac-address property.
33 $ref: /schemas/types.yaml#/definitions/uint8-array
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H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 segments of memory for buffering TX and RX, as well as the capability of
14 offloading TX/RX checksum calculation off the processor.
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
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H A Dfsl-fman.txt5 - FMan Node
6 - FMan Port Node
7 - FMan MURAM Node
8 - FMan dTSEC/XGEC/mEMAC Node
9 - FMan IEEE 1588 Node
10 - FMan MDIO Node
11 - Example
18 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
23 - compatible
32 - cell-index
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H A Dfsl,fman-dtsec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <madalin.bucur@nxp.com>
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
22 - fsl,fman-dtsec
23 - fsl,fman-xgec
24 - fsl,fman-memac
26 cell-index:
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H A Daltr,tse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Chevallier <maxime.chevallier@bootlin.com>
15 - const: altr,tse-1.0
16 - const: ALTR,tse-1.0
18 - const: altr,tse-msgdma-1.0
23 interrupt-names:
25 - const: rx_irq
26 - const: tx_irq
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/openbmc/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddpaa2-mac.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 #include <linux/pcs-lynx.h>
9 #include "dpaa2-eth.h"
10 #include "dpaa2-mac.h"
23 if (mac->ver_major == ver_major) in dpaa2_mac_cmp_ver()
24 return mac->ver_minor - ver_minor; in dpaa2_mac_cmp_ver()
25 return mac->ver_major - ver_major; in dpaa2_mac_cmp_ver()
30 mac->features = 0; in dpaa2_mac_detect_features()
34 mac->features |= DPAA2_MAC_FEATURE_PROTOCOL_CHANGE; in dpaa2_mac_detect_features()
61 return -EINVAL; in phy_mode()
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/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-ufs.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-ufs-v2.h"
25 #include "phy-qcom-qmp-pcs-ufs-v3.h"
26 #include "phy-qcom-qmp-pcs-ufs-v4.h"
27 #include "phy-qcom-qmp-pcs-ufs-v5.h"
28 #include "phy-qcom-qmp-pcs-ufs-v6.h"
30 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
68 /* set of registers with offsets different per-PHY */
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H A Dphy-qcom-qmp-pcie-msm8996.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
22 #include "phy-qcom-qmp.h"
66 /* set of registers with offsets different per-PHY */
73 /* PCS registers */
169 /* struct qmp_phy_cfg - per-PHY initialization config */
174 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
199 * struct qmp_phy - per-lane phy descriptor
205 * @rx: iomapped memory space for lane's rx
206 * @pcs: iomapped memory space for lane's pcs
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H A Dphy-qcom-qmp-pcie.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
25 #include "phy-qcom-qmp.h"
26 #include "phy-qcom-qmp-pcs-misc-v3.h"
27 #include "phy-qcom-qmp-pcs-pcie-v4.h"
28 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
29 #include "phy-qcom-qmp-pcs-pcie-v5.h"
30 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
31 #include "phy-qcom-qmp-pcs-pcie-v6.h"
32 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
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H A Dphy-qcom-qmp-usb-legacy.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-misc-v3.h"
25 #include "phy-qcom-qmp-pcs-usb-v4.h"
26 #include "phy-qcom-qmp-pcs-usb-v5.h"
89 /* set of registers with offsets different per-PHY */
91 /* PCS registers */
502 u16 pcs; member
505 u16 rx; member
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H A Dphy-qcom-qmp-usb.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
22 #include "phy-qcom-qmp.h"
23 #include "phy-qcom-qmp-pcs
1153 u16 pcs; global() member
1157 u16 rx; global() member
1207 void __iomem *pcs; global() member
1211 void __iomem *rx; global() member
1658 void __iomem *pcs = qmp->pcs; qmp_usb_init() local
1714 void __iomem *rx = qmp->rx; qmp_usb_power_on() local
1715 void __iomem *pcs = qmp->pcs; qmp_usb_power_on() local
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
18 #include <linux/pcs/pcs-xpcs.h>
47 /* TX and RX Descriptor Length, these need to be power of two.
49 * RX descriptor length less than 64 may cause inconsistent Rx chain error.
57 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
140 /* Tx/Rx IRQ error info */
150 /* Tx/Rx IRQ Events */
190 /* PCS */
269 /* PCS defines */
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/openbmc/linux/drivers/net/ethernet/sun/
H A Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */
31 #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */
34 #define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
48 #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
49 #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
50 #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
51 #define GREG_STAT_PCS 0x00002000 /* PCS signalled interrupt */
53 #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
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/openbmc/linux/include/uapi/linux/
H A Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
58 /* Media-dependent registers. */
59 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
60 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
61 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
62 * Lanes B-D are numbered 134-136. */
63 #define MDIO_PMA_10GBR_FSRT_CSR 147 /* 10GBASE-R fast retrain status and control */
64 #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
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/openbmc/u-boot/include/linux/
H A Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
24 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
52 /* Media-dependent registers. */
53 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
54 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
55 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
56 * Lanes B-D are numbered 134-136. */
57 #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
58 #define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
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H A Dfsl-ls1088a-ten64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
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/openbmc/linux/drivers/net/pcs/
H A Dpcs-xpcs-nxp.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/pcs/pcs-xpcs.h>
5 #include "pcs-xpcs.h"
67 /* In NXP SJA1105, the PCS is integrated with a PMA that has the TX lane
69 * normal non-inverted behavior, the TX lane polarity must be inverted in the
70 * PCS, via the DIGITAL_CONTROL_2 register.
126 /* Select PCS as transmitter data source. */ in nxp_sja1110_pma_config()
131 /* Program RX PLL feedback divider and reference divider for correct in nxp_sja1110_pma_config()
152 /* Enable TX and RX PLLs and circuits. in nxp_sja1110_pma_config()
153 * Release reset of PMA to enable data flow to/from PCS. in nxp_sja1110_pma_config()
[all …]
/openbmc/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
33 /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
36 /* VLAN Rx & Tx frame support. Default: disabled (cleared) */
39 /* Enable recognition of flow control frames on Rx. Default: enabled (set) */
122 /* Default TX/RX Threshold and delay timer values for SGDMA mode */
138 #define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */
139 #define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */
147 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
152 #define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */
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/openbmc/linux/drivers/net/ethernet/freescale/fman/
H A Dfman_dtsec.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
29 #define TBICON_AN_SENSE 0x0100 /* Auto-negotiation sense enable */
165 u32 tmr_ctrl; /* 0x020 Time-stamp Control register */
166 u32 tmr_pevent; /* 0x024 Time-stamp event register */
173 u32 igaddr[8]; /* 0x080-0x09C Individual/group address */
174 u32 gaddr[8]; /* 0x0A0-0x0BC Group address registers 0-7 */
179 u32 hafdup; /* 0x10C Half-duplex */
186 u32 exact_match1; /* octets 1-4 */
187 u32 exact_match2; /* octets 5-6 */
[all …]
H A Dfman_memac.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
14 #include <linux/pcs-lynx.h>
24 #define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */
56 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
57 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */
58 #define IF_MODE_MII 0x00000001 /* 30-31 MII interface */
59 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
62 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
63 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
[all …]
/openbmc/linux/drivers/net/ethernet/cadence/
H A Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
32 #define MACB_RBQP 0x0018 /* RX Q Base Address */
85 #define GEM_PBUFRXCUT 0x0044 /* RX Partial Store and Forward */
99 #define GEM_RXPTPUNI 0x00D4 /* PTP RX Unicast address */
113 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
114 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
115 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
116 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
117 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,msm8996-qmp-usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
17 qcom,sc8280xp-qmp-usb3-uni-phy.yaml.
22 - qcom,ipq6018-qmp-usb3-phy
23 - qcom,ipq8074-qmp-usb3-phy
24 - qcom,msm8996-qmp-usb3-phy
25 - qcom,msm8998-qmp-usb3-phy
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/openbmc/linux/drivers/net/ethernet/altera/
H A Daltera_tse_main.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
30 #include <linux/mdio/mdio-regmap.h>
36 #include <linux/pcs-lynx.h>
50 static int debug = -1;
52 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
61 MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list");
69 #define POLL_PHY (-1)
81 #define TSE_TX_THRESH(x) (x->tx_ring_size / 4)
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