1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Altera Triple-Speed Ethernet MAC driver
3  * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
4  *
5  * Contributors:
6  *   Dalon Westergreen
7  *   Thomas Chou
8  *   Ian Abbott
9  *   Yuriy Kozlov
10  *   Tobias Klauser
11  *   Andriy Smolskyy
12  *   Roman Bulgakov
13  *   Dmytro Mytarchuk
14  *   Matthew Gerlach
15  *
16  * Original driver contributed by SLS.
17  * Major updates contributed by GlobalLogic
18  */
19 
20 #include <linux/atomic.h>
21 #include <linux/delay.h>
22 #include <linux/etherdevice.h>
23 #include <linux/if_vlan.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/mii.h>
30 #include <linux/mdio/mdio-regmap.h>
31 #include <linux/netdevice.h>
32 #include <linux/of_device.h>
33 #include <linux/of_mdio.h>
34 #include <linux/of_net.h>
35 #include <linux/of_platform.h>
36 #include <linux/pcs-lynx.h>
37 #include <linux/phy.h>
38 #include <linux/platform_device.h>
39 #include <linux/regmap.h>
40 #include <linux/skbuff.h>
41 #include <asm/cacheflush.h>
42 
43 #include "altera_utils.h"
44 #include "altera_tse.h"
45 #include "altera_sgdma.h"
46 #include "altera_msgdma.h"
47 
48 static atomic_t instance_count = ATOMIC_INIT(~0);
49 /* Module parameters */
50 static int debug = -1;
51 module_param(debug, int, 0644);
52 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
53 
54 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
55 					NETIF_MSG_LINK | NETIF_MSG_IFUP |
56 					NETIF_MSG_IFDOWN);
57 
58 #define RX_DESCRIPTORS 64
59 static int dma_rx_num = RX_DESCRIPTORS;
60 module_param(dma_rx_num, int, 0644);
61 MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list");
62 
63 #define TX_DESCRIPTORS 64
64 static int dma_tx_num = TX_DESCRIPTORS;
65 module_param(dma_tx_num, int, 0644);
66 MODULE_PARM_DESC(dma_tx_num, "Number of descriptors in the TX list");
67 
68 
69 #define POLL_PHY (-1)
70 
71 /* Make sure DMA buffer size is larger than the max frame size
72  * plus some alignment offset and a VLAN header. If the max frame size is
73  * 1518, a VLAN header would be additional 4 bytes and additional
74  * headroom for alignment is 2 bytes, 2048 is just fine.
75  */
76 #define ALTERA_RXDMABUFFER_SIZE	2048
77 
78 /* Allow network stack to resume queuing packets after we've
79  * finished transmitting at least 1/4 of the packets in the queue.
80  */
81 #define TSE_TX_THRESH(x)	(x->tx_ring_size / 4)
82 
83 #define TXQUEUESTOP_THRESHHOLD	2
84 
85 static const struct of_device_id altera_tse_ids[];
86 
tse_tx_avail(struct altera_tse_private * priv)87 static inline u32 tse_tx_avail(struct altera_tse_private *priv)
88 {
89 	return priv->tx_cons + priv->tx_ring_size - priv->tx_prod - 1;
90 }
91 
92 /* MDIO specific functions
93  */
altera_tse_mdio_read(struct mii_bus * bus,int mii_id,int regnum)94 static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
95 {
96 	struct net_device *ndev = bus->priv;
97 	struct altera_tse_private *priv = netdev_priv(ndev);
98 
99 	/* set MDIO address */
100 	csrwr32((mii_id & 0x1f), priv->mac_dev,
101 		tse_csroffs(mdio_phy1_addr));
102 
103 	/* get the data */
104 	return csrrd32(priv->mac_dev,
105 		       tse_csroffs(mdio_phy1) + regnum * 4) & 0xffff;
106 }
107 
altera_tse_mdio_write(struct mii_bus * bus,int mii_id,int regnum,u16 value)108 static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
109 				 u16 value)
110 {
111 	struct net_device *ndev = bus->priv;
112 	struct altera_tse_private *priv = netdev_priv(ndev);
113 
114 	/* set MDIO address */
115 	csrwr32((mii_id & 0x1f), priv->mac_dev,
116 		tse_csroffs(mdio_phy1_addr));
117 
118 	/* write the data */
119 	csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4);
120 	return 0;
121 }
122 
altera_tse_mdio_create(struct net_device * dev,unsigned int id)123 static int altera_tse_mdio_create(struct net_device *dev, unsigned int id)
124 {
125 	struct altera_tse_private *priv = netdev_priv(dev);
126 	struct device_node *mdio_node = NULL;
127 	struct device_node *child_node = NULL;
128 	struct mii_bus *mdio = NULL;
129 	int ret;
130 
131 	for_each_child_of_node(priv->device->of_node, child_node) {
132 		if (of_device_is_compatible(child_node, "altr,tse-mdio")) {
133 			mdio_node = child_node;
134 			break;
135 		}
136 	}
137 
138 	if (mdio_node) {
139 		netdev_dbg(dev, "FOUND MDIO subnode\n");
140 	} else {
141 		netdev_dbg(dev, "NO MDIO subnode\n");
142 		return 0;
143 	}
144 
145 	mdio = mdiobus_alloc();
146 	if (mdio == NULL) {
147 		netdev_err(dev, "Error allocating MDIO bus\n");
148 		ret = -ENOMEM;
149 		goto put_node;
150 	}
151 
152 	mdio->name = ALTERA_TSE_RESOURCE_NAME;
153 	mdio->read = &altera_tse_mdio_read;
154 	mdio->write = &altera_tse_mdio_write;
155 	snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id);
156 
157 	mdio->priv = dev;
158 	mdio->parent = priv->device;
159 
160 	ret = of_mdiobus_register(mdio, mdio_node);
161 	if (ret != 0) {
162 		netdev_err(dev, "Cannot register MDIO bus %s\n",
163 			   mdio->id);
164 		goto out_free_mdio;
165 	}
166 	of_node_put(mdio_node);
167 
168 	if (netif_msg_drv(priv))
169 		netdev_info(dev, "MDIO bus %s: created\n", mdio->id);
170 
171 	priv->mdio = mdio;
172 	return 0;
173 out_free_mdio:
174 	mdiobus_free(mdio);
175 	mdio = NULL;
176 put_node:
177 	of_node_put(mdio_node);
178 	return ret;
179 }
180 
altera_tse_mdio_destroy(struct net_device * dev)181 static void altera_tse_mdio_destroy(struct net_device *dev)
182 {
183 	struct altera_tse_private *priv = netdev_priv(dev);
184 
185 	if (priv->mdio == NULL)
186 		return;
187 
188 	if (netif_msg_drv(priv))
189 		netdev_info(dev, "MDIO bus %s: removed\n",
190 			    priv->mdio->id);
191 
192 	mdiobus_unregister(priv->mdio);
193 	mdiobus_free(priv->mdio);
194 	priv->mdio = NULL;
195 }
196 
tse_init_rx_buffer(struct altera_tse_private * priv,struct tse_buffer * rxbuffer,int len)197 static int tse_init_rx_buffer(struct altera_tse_private *priv,
198 			      struct tse_buffer *rxbuffer, int len)
199 {
200 	rxbuffer->skb = netdev_alloc_skb_ip_align(priv->dev, len);
201 	if (!rxbuffer->skb)
202 		return -ENOMEM;
203 
204 	rxbuffer->dma_addr = dma_map_single(priv->device, rxbuffer->skb->data,
205 						len,
206 						DMA_FROM_DEVICE);
207 
208 	if (dma_mapping_error(priv->device, rxbuffer->dma_addr)) {
209 		netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
210 		dev_kfree_skb_any(rxbuffer->skb);
211 		return -EINVAL;
212 	}
213 	rxbuffer->dma_addr &= (dma_addr_t)~3;
214 	rxbuffer->len = len;
215 	return 0;
216 }
217 
tse_free_rx_buffer(struct altera_tse_private * priv,struct tse_buffer * rxbuffer)218 static void tse_free_rx_buffer(struct altera_tse_private *priv,
219 			       struct tse_buffer *rxbuffer)
220 {
221 	dma_addr_t dma_addr = rxbuffer->dma_addr;
222 	struct sk_buff *skb = rxbuffer->skb;
223 
224 	if (skb != NULL) {
225 		if (dma_addr)
226 			dma_unmap_single(priv->device, dma_addr,
227 					 rxbuffer->len,
228 					 DMA_FROM_DEVICE);
229 		dev_kfree_skb_any(skb);
230 		rxbuffer->skb = NULL;
231 		rxbuffer->dma_addr = 0;
232 	}
233 }
234 
235 /* Unmap and free Tx buffer resources
236  */
tse_free_tx_buffer(struct altera_tse_private * priv,struct tse_buffer * buffer)237 static void tse_free_tx_buffer(struct altera_tse_private *priv,
238 			       struct tse_buffer *buffer)
239 {
240 	if (buffer->dma_addr) {
241 		if (buffer->mapped_as_page)
242 			dma_unmap_page(priv->device, buffer->dma_addr,
243 				       buffer->len, DMA_TO_DEVICE);
244 		else
245 			dma_unmap_single(priv->device, buffer->dma_addr,
246 					 buffer->len, DMA_TO_DEVICE);
247 		buffer->dma_addr = 0;
248 	}
249 	if (buffer->skb) {
250 		dev_kfree_skb_any(buffer->skb);
251 		buffer->skb = NULL;
252 	}
253 }
254 
alloc_init_skbufs(struct altera_tse_private * priv)255 static int alloc_init_skbufs(struct altera_tse_private *priv)
256 {
257 	unsigned int rx_descs = priv->rx_ring_size;
258 	unsigned int tx_descs = priv->tx_ring_size;
259 	int ret = -ENOMEM;
260 	int i;
261 
262 	/* Create Rx ring buffer */
263 	priv->rx_ring = kcalloc(rx_descs, sizeof(struct tse_buffer),
264 				GFP_KERNEL);
265 	if (!priv->rx_ring)
266 		goto err_rx_ring;
267 
268 	/* Create Tx ring buffer */
269 	priv->tx_ring = kcalloc(tx_descs, sizeof(struct tse_buffer),
270 				GFP_KERNEL);
271 	if (!priv->tx_ring)
272 		goto err_tx_ring;
273 
274 	priv->tx_cons = 0;
275 	priv->tx_prod = 0;
276 
277 	/* Init Rx ring */
278 	for (i = 0; i < rx_descs; i++) {
279 		ret = tse_init_rx_buffer(priv, &priv->rx_ring[i],
280 					 priv->rx_dma_buf_sz);
281 		if (ret)
282 			goto err_init_rx_buffers;
283 	}
284 
285 	priv->rx_cons = 0;
286 	priv->rx_prod = 0;
287 
288 	return 0;
289 err_init_rx_buffers:
290 	while (--i >= 0)
291 		tse_free_rx_buffer(priv, &priv->rx_ring[i]);
292 	kfree(priv->tx_ring);
293 err_tx_ring:
294 	kfree(priv->rx_ring);
295 err_rx_ring:
296 	return ret;
297 }
298 
free_skbufs(struct net_device * dev)299 static void free_skbufs(struct net_device *dev)
300 {
301 	struct altera_tse_private *priv = netdev_priv(dev);
302 	unsigned int rx_descs = priv->rx_ring_size;
303 	unsigned int tx_descs = priv->tx_ring_size;
304 	int i;
305 
306 	/* Release the DMA TX/RX socket buffers */
307 	for (i = 0; i < rx_descs; i++)
308 		tse_free_rx_buffer(priv, &priv->rx_ring[i]);
309 	for (i = 0; i < tx_descs; i++)
310 		tse_free_tx_buffer(priv, &priv->tx_ring[i]);
311 
312 
313 	kfree(priv->tx_ring);
314 }
315 
316 /* Reallocate the skb for the reception process
317  */
tse_rx_refill(struct altera_tse_private * priv)318 static inline void tse_rx_refill(struct altera_tse_private *priv)
319 {
320 	unsigned int rxsize = priv->rx_ring_size;
321 	unsigned int entry;
322 	int ret;
323 
324 	for (; priv->rx_cons - priv->rx_prod > 0;
325 			priv->rx_prod++) {
326 		entry = priv->rx_prod % rxsize;
327 		if (likely(priv->rx_ring[entry].skb == NULL)) {
328 			ret = tse_init_rx_buffer(priv, &priv->rx_ring[entry],
329 				priv->rx_dma_buf_sz);
330 			if (unlikely(ret != 0))
331 				break;
332 			priv->dmaops->add_rx_desc(priv, &priv->rx_ring[entry]);
333 		}
334 	}
335 }
336 
337 /* Pull out the VLAN tag and fix up the packet
338  */
tse_rx_vlan(struct net_device * dev,struct sk_buff * skb)339 static inline void tse_rx_vlan(struct net_device *dev, struct sk_buff *skb)
340 {
341 	struct ethhdr *eth_hdr;
342 	u16 vid;
343 
344 	if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
345 	    !__vlan_get_tag(skb, &vid)) {
346 		eth_hdr = (struct ethhdr *)skb->data;
347 		memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2);
348 		skb_pull(skb, VLAN_HLEN);
349 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
350 	}
351 }
352 
353 /* Receive a packet: retrieve and pass over to upper levels
354  */
tse_rx(struct altera_tse_private * priv,int limit)355 static int tse_rx(struct altera_tse_private *priv, int limit)
356 {
357 	unsigned int entry = priv->rx_cons % priv->rx_ring_size;
358 	unsigned int next_entry;
359 	unsigned int count = 0;
360 	struct sk_buff *skb;
361 	u32 rxstatus;
362 	u16 pktlength;
363 	u16 pktstatus;
364 
365 	/* Check for count < limit first as get_rx_status is changing
366 	* the response-fifo so we must process the next packet
367 	* after calling get_rx_status if a response is pending.
368 	* (reading the last byte of the response pops the value from the fifo.)
369 	*/
370 	while ((count < limit) &&
371 	       ((rxstatus = priv->dmaops->get_rx_status(priv)) != 0)) {
372 		pktstatus = rxstatus >> 16;
373 		pktlength = rxstatus & 0xffff;
374 
375 		if ((pktstatus & 0xFF) || (pktlength == 0))
376 			netdev_err(priv->dev,
377 				   "RCV pktstatus %08X pktlength %08X\n",
378 				   pktstatus, pktlength);
379 
380 		/* DMA transfer from TSE starts with 2 additional bytes for
381 		 * IP payload alignment. Status returned by get_rx_status()
382 		 * contains DMA transfer length. Packet is 2 bytes shorter.
383 		 */
384 		pktlength -= 2;
385 
386 		count++;
387 		next_entry = (++priv->rx_cons) % priv->rx_ring_size;
388 
389 		skb = priv->rx_ring[entry].skb;
390 		if (unlikely(!skb)) {
391 			netdev_err(priv->dev,
392 				   "%s: Inconsistent Rx descriptor chain\n",
393 				   __func__);
394 			priv->dev->stats.rx_dropped++;
395 			break;
396 		}
397 		priv->rx_ring[entry].skb = NULL;
398 
399 		skb_put(skb, pktlength);
400 
401 		dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr,
402 				 priv->rx_ring[entry].len, DMA_FROM_DEVICE);
403 
404 		if (netif_msg_pktdata(priv)) {
405 			netdev_info(priv->dev, "frame received %d bytes\n",
406 				    pktlength);
407 			print_hex_dump(KERN_ERR, "data: ", DUMP_PREFIX_OFFSET,
408 				       16, 1, skb->data, pktlength, true);
409 		}
410 
411 		tse_rx_vlan(priv->dev, skb);
412 
413 		skb->protocol = eth_type_trans(skb, priv->dev);
414 		skb_checksum_none_assert(skb);
415 
416 		napi_gro_receive(&priv->napi, skb);
417 
418 		priv->dev->stats.rx_packets++;
419 		priv->dev->stats.rx_bytes += pktlength;
420 
421 		entry = next_entry;
422 
423 		tse_rx_refill(priv);
424 	}
425 
426 	return count;
427 }
428 
429 /* Reclaim resources after transmission completes
430  */
tse_tx_complete(struct altera_tse_private * priv)431 static int tse_tx_complete(struct altera_tse_private *priv)
432 {
433 	unsigned int txsize = priv->tx_ring_size;
434 	struct tse_buffer *tx_buff;
435 	unsigned int entry;
436 	int txcomplete = 0;
437 	u32 ready;
438 
439 	spin_lock(&priv->tx_lock);
440 
441 	ready = priv->dmaops->tx_completions(priv);
442 
443 	/* Free sent buffers */
444 	while (ready && (priv->tx_cons != priv->tx_prod)) {
445 		entry = priv->tx_cons % txsize;
446 		tx_buff = &priv->tx_ring[entry];
447 
448 		if (netif_msg_tx_done(priv))
449 			netdev_dbg(priv->dev, "%s: curr %d, dirty %d\n",
450 				   __func__, priv->tx_prod, priv->tx_cons);
451 
452 		if (likely(tx_buff->skb))
453 			priv->dev->stats.tx_packets++;
454 
455 		tse_free_tx_buffer(priv, tx_buff);
456 		priv->tx_cons++;
457 
458 		txcomplete++;
459 		ready--;
460 	}
461 
462 	if (unlikely(netif_queue_stopped(priv->dev) &&
463 		     tse_tx_avail(priv) > TSE_TX_THRESH(priv))) {
464 		if (netif_queue_stopped(priv->dev) &&
465 		    tse_tx_avail(priv) > TSE_TX_THRESH(priv)) {
466 			if (netif_msg_tx_done(priv))
467 				netdev_dbg(priv->dev, "%s: restart transmit\n",
468 					   __func__);
469 			netif_wake_queue(priv->dev);
470 		}
471 	}
472 
473 	spin_unlock(&priv->tx_lock);
474 	return txcomplete;
475 }
476 
477 /* NAPI polling function
478  */
tse_poll(struct napi_struct * napi,int budget)479 static int tse_poll(struct napi_struct *napi, int budget)
480 {
481 	struct altera_tse_private *priv =
482 			container_of(napi, struct altera_tse_private, napi);
483 	unsigned long int flags;
484 	int rxcomplete = 0;
485 
486 	tse_tx_complete(priv);
487 
488 	rxcomplete = tse_rx(priv, budget);
489 
490 	if (rxcomplete < budget) {
491 
492 		napi_complete_done(napi, rxcomplete);
493 
494 		netdev_dbg(priv->dev,
495 			   "NAPI Complete, did %d packets with budget %d\n",
496 			   rxcomplete, budget);
497 
498 		spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
499 		priv->dmaops->enable_rxirq(priv);
500 		priv->dmaops->enable_txirq(priv);
501 		spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
502 	}
503 	return rxcomplete;
504 }
505 
506 /* DMA TX & RX FIFO interrupt routing
507  */
altera_isr(int irq,void * dev_id)508 static irqreturn_t altera_isr(int irq, void *dev_id)
509 {
510 	struct net_device *dev = dev_id;
511 	struct altera_tse_private *priv;
512 
513 	if (unlikely(!dev)) {
514 		pr_err("%s: invalid dev pointer\n", __func__);
515 		return IRQ_NONE;
516 	}
517 	priv = netdev_priv(dev);
518 
519 	spin_lock(&priv->rxdma_irq_lock);
520 	/* reset IRQs */
521 	priv->dmaops->clear_rxirq(priv);
522 	priv->dmaops->clear_txirq(priv);
523 	spin_unlock(&priv->rxdma_irq_lock);
524 
525 	if (likely(napi_schedule_prep(&priv->napi))) {
526 		spin_lock(&priv->rxdma_irq_lock);
527 		priv->dmaops->disable_rxirq(priv);
528 		priv->dmaops->disable_txirq(priv);
529 		spin_unlock(&priv->rxdma_irq_lock);
530 		__napi_schedule(&priv->napi);
531 	}
532 
533 
534 	return IRQ_HANDLED;
535 }
536 
537 /* Transmit a packet (called by the kernel). Dispatches
538  * either the SGDMA method for transmitting or the
539  * MSGDMA method, assumes no scatter/gather support,
540  * implying an assumption that there's only one
541  * physically contiguous fragment starting at
542  * skb->data, for length of skb_headlen(skb).
543  */
tse_start_xmit(struct sk_buff * skb,struct net_device * dev)544 static netdev_tx_t tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
545 {
546 	struct altera_tse_private *priv = netdev_priv(dev);
547 	unsigned int nopaged_len = skb_headlen(skb);
548 	unsigned int txsize = priv->tx_ring_size;
549 	int nfrags = skb_shinfo(skb)->nr_frags;
550 	struct tse_buffer *buffer = NULL;
551 	netdev_tx_t ret = NETDEV_TX_OK;
552 	dma_addr_t dma_addr;
553 	unsigned int entry;
554 
555 	spin_lock_bh(&priv->tx_lock);
556 
557 	if (unlikely(tse_tx_avail(priv) < nfrags + 1)) {
558 		if (!netif_queue_stopped(dev)) {
559 			netif_stop_queue(dev);
560 			/* This is a hard error, log it. */
561 			netdev_err(priv->dev,
562 				   "%s: Tx list full when queue awake\n",
563 				   __func__);
564 		}
565 		ret = NETDEV_TX_BUSY;
566 		goto out;
567 	}
568 
569 	/* Map the first skb fragment */
570 	entry = priv->tx_prod % txsize;
571 	buffer = &priv->tx_ring[entry];
572 
573 	dma_addr = dma_map_single(priv->device, skb->data, nopaged_len,
574 				  DMA_TO_DEVICE);
575 	if (dma_mapping_error(priv->device, dma_addr)) {
576 		netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
577 		ret = NETDEV_TX_OK;
578 		goto out;
579 	}
580 
581 	buffer->skb = skb;
582 	buffer->dma_addr = dma_addr;
583 	buffer->len = nopaged_len;
584 
585 	priv->dmaops->tx_buffer(priv, buffer);
586 
587 	skb_tx_timestamp(skb);
588 
589 	priv->tx_prod++;
590 	dev->stats.tx_bytes += skb->len;
591 
592 	if (unlikely(tse_tx_avail(priv) <= TXQUEUESTOP_THRESHHOLD)) {
593 		if (netif_msg_hw(priv))
594 			netdev_dbg(priv->dev, "%s: stop transmitted packets\n",
595 				   __func__);
596 		netif_stop_queue(dev);
597 	}
598 
599 out:
600 	spin_unlock_bh(&priv->tx_lock);
601 
602 	return ret;
603 }
604 
altera_tse_phy_get_addr_mdio_create(struct net_device * dev)605 static int altera_tse_phy_get_addr_mdio_create(struct net_device *dev)
606 {
607 	struct altera_tse_private *priv = netdev_priv(dev);
608 	struct device_node *np = priv->device->of_node;
609 	int ret;
610 
611 	ret = of_get_phy_mode(np, &priv->phy_iface);
612 
613 	/* Avoid get phy addr and create mdio if no phy is present */
614 	if (ret)
615 		return 0;
616 
617 	/* try to get PHY address from device tree, use PHY autodetection if
618 	 * no valid address is given
619 	 */
620 
621 	if (of_property_read_u32(priv->device->of_node, "phy-addr",
622 			 &priv->phy_addr)) {
623 		priv->phy_addr = POLL_PHY;
624 	}
625 
626 	if (!((priv->phy_addr == POLL_PHY) ||
627 		  ((priv->phy_addr >= 0) && (priv->phy_addr < PHY_MAX_ADDR)))) {
628 		netdev_err(dev, "invalid phy-addr specified %d\n",
629 			priv->phy_addr);
630 		return -ENODEV;
631 	}
632 
633 	/* Create/attach to MDIO bus */
634 	ret = altera_tse_mdio_create(dev,
635 					 atomic_add_return(1, &instance_count));
636 
637 	if (ret)
638 		return -ENODEV;
639 
640 	return 0;
641 }
642 
tse_update_mac_addr(struct altera_tse_private * priv,const u8 * addr)643 static void tse_update_mac_addr(struct altera_tse_private *priv, const u8 *addr)
644 {
645 	u32 msb;
646 	u32 lsb;
647 
648 	msb = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
649 	lsb = ((addr[5] << 8) | addr[4]) & 0xffff;
650 
651 	/* Set primary MAC address */
652 	csrwr32(msb, priv->mac_dev, tse_csroffs(mac_addr_0));
653 	csrwr32(lsb, priv->mac_dev, tse_csroffs(mac_addr_1));
654 }
655 
656 /* MAC software reset.
657  * When reset is triggered, the MAC function completes the current
658  * transmission or reception, and subsequently disables the transmit and
659  * receive logic, flushes the receive FIFO buffer, and resets the statistics
660  * counters.
661  */
reset_mac(struct altera_tse_private * priv)662 static int reset_mac(struct altera_tse_private *priv)
663 {
664 	int counter;
665 	u32 dat;
666 
667 	dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
668 	dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
669 	dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET;
670 	csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
671 
672 	counter = 0;
673 	while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
674 		if (tse_bit_is_clear(priv->mac_dev, tse_csroffs(command_config),
675 				     MAC_CMDCFG_SW_RESET))
676 			break;
677 		udelay(1);
678 	}
679 
680 	if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
681 		dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
682 		dat &= ~MAC_CMDCFG_SW_RESET;
683 		csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
684 		return -1;
685 	}
686 	return 0;
687 }
688 
689 /* Initialize MAC core registers
690 */
init_mac(struct altera_tse_private * priv)691 static int init_mac(struct altera_tse_private *priv)
692 {
693 	unsigned int cmd = 0;
694 	u32 frm_length;
695 
696 	/* Setup Rx FIFO */
697 	csrwr32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY,
698 		priv->mac_dev, tse_csroffs(rx_section_empty));
699 
700 	csrwr32(ALTERA_TSE_RX_SECTION_FULL, priv->mac_dev,
701 		tse_csroffs(rx_section_full));
702 
703 	csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY, priv->mac_dev,
704 		tse_csroffs(rx_almost_empty));
705 
706 	csrwr32(ALTERA_TSE_RX_ALMOST_FULL, priv->mac_dev,
707 		tse_csroffs(rx_almost_full));
708 
709 	/* Setup Tx FIFO */
710 	csrwr32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY,
711 		priv->mac_dev, tse_csroffs(tx_section_empty));
712 
713 	csrwr32(ALTERA_TSE_TX_SECTION_FULL, priv->mac_dev,
714 		tse_csroffs(tx_section_full));
715 
716 	csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY, priv->mac_dev,
717 		tse_csroffs(tx_almost_empty));
718 
719 	csrwr32(ALTERA_TSE_TX_ALMOST_FULL, priv->mac_dev,
720 		tse_csroffs(tx_almost_full));
721 
722 	/* MAC Address Configuration */
723 	tse_update_mac_addr(priv, priv->dev->dev_addr);
724 
725 	/* MAC Function Configuration */
726 	frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN;
727 	csrwr32(frm_length, priv->mac_dev, tse_csroffs(frm_length));
728 
729 	csrwr32(ALTERA_TSE_TX_IPG_LENGTH, priv->mac_dev,
730 		tse_csroffs(tx_ipg_length));
731 
732 	/* Disable RX/TX shift 16 for alignment of all received frames on 16-bit
733 	 * start address
734 	 */
735 	tse_set_bit(priv->mac_dev, tse_csroffs(rx_cmd_stat),
736 		    ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16);
737 
738 	tse_clear_bit(priv->mac_dev, tse_csroffs(tx_cmd_stat),
739 		      ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 |
740 		      ALTERA_TSE_TX_CMD_STAT_OMIT_CRC);
741 
742 	/* Set the MAC options */
743 	cmd = csrrd32(priv->mac_dev, tse_csroffs(command_config));
744 	cmd &= ~MAC_CMDCFG_PAD_EN;	/* No padding Removal on Receive */
745 	cmd &= ~MAC_CMDCFG_CRC_FWD;	/* CRC Removal */
746 	cmd |= MAC_CMDCFG_RX_ERR_DISC;	/* Automatically discard frames
747 					 * with CRC errors
748 					 */
749 	cmd |= MAC_CMDCFG_CNTL_FRM_ENA;
750 	cmd &= ~MAC_CMDCFG_TX_ENA;
751 	cmd &= ~MAC_CMDCFG_RX_ENA;
752 
753 	/* Default speed and duplex setting, full/100 */
754 	cmd &= ~MAC_CMDCFG_HD_ENA;
755 	cmd &= ~MAC_CMDCFG_ETH_SPEED;
756 	cmd &= ~MAC_CMDCFG_ENA_10;
757 
758 	csrwr32(cmd, priv->mac_dev, tse_csroffs(command_config));
759 
760 	csrwr32(ALTERA_TSE_PAUSE_QUANTA, priv->mac_dev,
761 		tse_csroffs(pause_quanta));
762 
763 	if (netif_msg_hw(priv))
764 		dev_dbg(priv->device,
765 			"MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd);
766 
767 	return 0;
768 }
769 
770 /* Start/stop MAC transmission logic
771  */
tse_set_mac(struct altera_tse_private * priv,bool enable)772 static void tse_set_mac(struct altera_tse_private *priv, bool enable)
773 {
774 	u32 value = csrrd32(priv->mac_dev, tse_csroffs(command_config));
775 
776 	if (enable)
777 		value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA;
778 	else
779 		value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
780 
781 	csrwr32(value, priv->mac_dev, tse_csroffs(command_config));
782 }
783 
784 /* Change the MTU
785  */
tse_change_mtu(struct net_device * dev,int new_mtu)786 static int tse_change_mtu(struct net_device *dev, int new_mtu)
787 {
788 	if (netif_running(dev)) {
789 		netdev_err(dev, "must be stopped to change its MTU\n");
790 		return -EBUSY;
791 	}
792 
793 	dev->mtu = new_mtu;
794 	netdev_update_features(dev);
795 
796 	return 0;
797 }
798 
altera_tse_set_mcfilter(struct net_device * dev)799 static void altera_tse_set_mcfilter(struct net_device *dev)
800 {
801 	struct altera_tse_private *priv = netdev_priv(dev);
802 	struct netdev_hw_addr *ha;
803 	int i;
804 
805 	/* clear the hash filter */
806 	for (i = 0; i < 64; i++)
807 		csrwr32(0, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
808 
809 	netdev_for_each_mc_addr(ha, dev) {
810 		unsigned int hash = 0;
811 		int mac_octet;
812 
813 		for (mac_octet = 5; mac_octet >= 0; mac_octet--) {
814 			unsigned char xor_bit = 0;
815 			unsigned char octet = ha->addr[mac_octet];
816 			unsigned int bitshift;
817 
818 			for (bitshift = 0; bitshift < 8; bitshift++)
819 				xor_bit ^= ((octet >> bitshift) & 0x01);
820 
821 			hash = (hash << 1) | xor_bit;
822 		}
823 		csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + hash * 4);
824 	}
825 }
826 
827 
altera_tse_set_mcfilterall(struct net_device * dev)828 static void altera_tse_set_mcfilterall(struct net_device *dev)
829 {
830 	struct altera_tse_private *priv = netdev_priv(dev);
831 	int i;
832 
833 	/* set the hash filter */
834 	for (i = 0; i < 64; i++)
835 		csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
836 }
837 
838 /* Set or clear the multicast filter for this adapter
839  */
tse_set_rx_mode_hashfilter(struct net_device * dev)840 static void tse_set_rx_mode_hashfilter(struct net_device *dev)
841 {
842 	struct altera_tse_private *priv = netdev_priv(dev);
843 
844 	spin_lock(&priv->mac_cfg_lock);
845 
846 	if (dev->flags & IFF_PROMISC)
847 		tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
848 			    MAC_CMDCFG_PROMIS_EN);
849 
850 	if (dev->flags & IFF_ALLMULTI)
851 		altera_tse_set_mcfilterall(dev);
852 	else
853 		altera_tse_set_mcfilter(dev);
854 
855 	spin_unlock(&priv->mac_cfg_lock);
856 }
857 
858 /* Set or clear the multicast filter for this adapter
859  */
tse_set_rx_mode(struct net_device * dev)860 static void tse_set_rx_mode(struct net_device *dev)
861 {
862 	struct altera_tse_private *priv = netdev_priv(dev);
863 
864 	spin_lock(&priv->mac_cfg_lock);
865 
866 	if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) ||
867 	    !netdev_mc_empty(dev) || !netdev_uc_empty(dev))
868 		tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
869 			    MAC_CMDCFG_PROMIS_EN);
870 	else
871 		tse_clear_bit(priv->mac_dev, tse_csroffs(command_config),
872 			      MAC_CMDCFG_PROMIS_EN);
873 
874 	spin_unlock(&priv->mac_cfg_lock);
875 }
876 
877 /* Open and initialize the interface
878  */
tse_open(struct net_device * dev)879 static int tse_open(struct net_device *dev)
880 {
881 	struct altera_tse_private *priv = netdev_priv(dev);
882 	unsigned long flags;
883 	int ret = 0;
884 	int i;
885 
886 	/* Reset and configure TSE MAC and probe associated PHY */
887 	ret = priv->dmaops->init_dma(priv);
888 	if (ret != 0) {
889 		netdev_err(dev, "Cannot initialize DMA\n");
890 		goto phy_error;
891 	}
892 
893 	if (netif_msg_ifup(priv))
894 		netdev_warn(dev, "device MAC address %pM\n",
895 			    dev->dev_addr);
896 
897 	if ((priv->revision < 0xd00) || (priv->revision > 0xe00))
898 		netdev_warn(dev, "TSE revision %x\n", priv->revision);
899 
900 	spin_lock(&priv->mac_cfg_lock);
901 
902 	ret = reset_mac(priv);
903 	/* Note that reset_mac will fail if the clocks are gated by the PHY
904 	 * due to the PHY being put into isolation or power down mode.
905 	 * This is not an error if reset fails due to no clock.
906 	 */
907 	if (ret)
908 		netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
909 
910 	ret = init_mac(priv);
911 	spin_unlock(&priv->mac_cfg_lock);
912 	if (ret) {
913 		netdev_err(dev, "Cannot init MAC core (error: %d)\n", ret);
914 		goto alloc_skbuf_error;
915 	}
916 
917 	priv->dmaops->reset_dma(priv);
918 
919 	/* Create and initialize the TX/RX descriptors chains. */
920 	priv->rx_ring_size = dma_rx_num;
921 	priv->tx_ring_size = dma_tx_num;
922 	ret = alloc_init_skbufs(priv);
923 	if (ret) {
924 		netdev_err(dev, "DMA descriptors initialization failed\n");
925 		goto alloc_skbuf_error;
926 	}
927 
928 
929 	/* Register RX interrupt */
930 	ret = request_irq(priv->rx_irq, altera_isr, IRQF_SHARED,
931 			  dev->name, dev);
932 	if (ret) {
933 		netdev_err(dev, "Unable to register RX interrupt %d\n",
934 			   priv->rx_irq);
935 		goto init_error;
936 	}
937 
938 	/* Register TX interrupt */
939 	ret = request_irq(priv->tx_irq, altera_isr, IRQF_SHARED,
940 			  dev->name, dev);
941 	if (ret) {
942 		netdev_err(dev, "Unable to register TX interrupt %d\n",
943 			   priv->tx_irq);
944 		goto tx_request_irq_error;
945 	}
946 
947 	/* Enable DMA interrupts */
948 	spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
949 	priv->dmaops->enable_rxirq(priv);
950 	priv->dmaops->enable_txirq(priv);
951 
952 	/* Setup RX descriptor chain */
953 	for (i = 0; i < priv->rx_ring_size; i++)
954 		priv->dmaops->add_rx_desc(priv, &priv->rx_ring[i]);
955 
956 	spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
957 
958 	ret = phylink_of_phy_connect(priv->phylink, priv->device->of_node, 0);
959 	if (ret) {
960 		netdev_err(dev, "could not connect phylink (%d)\n", ret);
961 		goto tx_request_irq_error;
962 	}
963 	phylink_start(priv->phylink);
964 
965 	napi_enable(&priv->napi);
966 	netif_start_queue(dev);
967 
968 	priv->dmaops->start_rxdma(priv);
969 
970 	/* Start MAC Rx/Tx */
971 	spin_lock(&priv->mac_cfg_lock);
972 	tse_set_mac(priv, true);
973 	spin_unlock(&priv->mac_cfg_lock);
974 
975 	return 0;
976 
977 tx_request_irq_error:
978 	free_irq(priv->rx_irq, dev);
979 init_error:
980 	free_skbufs(dev);
981 alloc_skbuf_error:
982 phy_error:
983 	return ret;
984 }
985 
986 /* Stop TSE MAC interface and put the device in an inactive state
987  */
tse_shutdown(struct net_device * dev)988 static int tse_shutdown(struct net_device *dev)
989 {
990 	struct altera_tse_private *priv = netdev_priv(dev);
991 	unsigned long int flags;
992 	int ret;
993 
994 	phylink_stop(priv->phylink);
995 	phylink_disconnect_phy(priv->phylink);
996 	netif_stop_queue(dev);
997 	napi_disable(&priv->napi);
998 
999 	/* Disable DMA interrupts */
1000 	spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1001 	priv->dmaops->disable_rxirq(priv);
1002 	priv->dmaops->disable_txirq(priv);
1003 	spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1004 
1005 	/* Free the IRQ lines */
1006 	free_irq(priv->rx_irq, dev);
1007 	free_irq(priv->tx_irq, dev);
1008 
1009 	/* disable and reset the MAC, empties fifo */
1010 	spin_lock(&priv->mac_cfg_lock);
1011 	spin_lock(&priv->tx_lock);
1012 
1013 	ret = reset_mac(priv);
1014 	/* Note that reset_mac will fail if the clocks are gated by the PHY
1015 	 * due to the PHY being put into isolation or power down mode.
1016 	 * This is not an error if reset fails due to no clock.
1017 	 */
1018 	if (ret)
1019 		netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1020 	priv->dmaops->reset_dma(priv);
1021 	free_skbufs(dev);
1022 
1023 	spin_unlock(&priv->tx_lock);
1024 	spin_unlock(&priv->mac_cfg_lock);
1025 
1026 	priv->dmaops->uninit_dma(priv);
1027 
1028 	return 0;
1029 }
1030 
1031 static struct net_device_ops altera_tse_netdev_ops = {
1032 	.ndo_open		= tse_open,
1033 	.ndo_stop		= tse_shutdown,
1034 	.ndo_start_xmit		= tse_start_xmit,
1035 	.ndo_set_mac_address	= eth_mac_addr,
1036 	.ndo_set_rx_mode	= tse_set_rx_mode,
1037 	.ndo_change_mtu		= tse_change_mtu,
1038 	.ndo_validate_addr	= eth_validate_addr,
1039 };
1040 
alt_tse_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)1041 static void alt_tse_mac_config(struct phylink_config *config, unsigned int mode,
1042 			       const struct phylink_link_state *state)
1043 {
1044 	struct net_device *ndev = to_net_dev(config->dev);
1045 	struct altera_tse_private *priv = netdev_priv(ndev);
1046 
1047 	spin_lock(&priv->mac_cfg_lock);
1048 	reset_mac(priv);
1049 	tse_set_mac(priv, true);
1050 	spin_unlock(&priv->mac_cfg_lock);
1051 }
1052 
alt_tse_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)1053 static void alt_tse_mac_link_down(struct phylink_config *config,
1054 				  unsigned int mode, phy_interface_t interface)
1055 {
1056 }
1057 
alt_tse_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)1058 static void alt_tse_mac_link_up(struct phylink_config *config,
1059 				struct phy_device *phy, unsigned int mode,
1060 				phy_interface_t interface, int speed,
1061 				int duplex, bool tx_pause, bool rx_pause)
1062 {
1063 	struct net_device *ndev = to_net_dev(config->dev);
1064 	struct altera_tse_private *priv = netdev_priv(ndev);
1065 	u32 ctrl;
1066 
1067 	ctrl = csrrd32(priv->mac_dev, tse_csroffs(command_config));
1068 	ctrl &= ~(MAC_CMDCFG_ENA_10 | MAC_CMDCFG_ETH_SPEED | MAC_CMDCFG_HD_ENA);
1069 
1070 	if (duplex == DUPLEX_HALF)
1071 		ctrl |= MAC_CMDCFG_HD_ENA;
1072 
1073 	if (speed == SPEED_1000)
1074 		ctrl |= MAC_CMDCFG_ETH_SPEED;
1075 	else if (speed == SPEED_10)
1076 		ctrl |= MAC_CMDCFG_ENA_10;
1077 
1078 	spin_lock(&priv->mac_cfg_lock);
1079 	csrwr32(ctrl, priv->mac_dev, tse_csroffs(command_config));
1080 	spin_unlock(&priv->mac_cfg_lock);
1081 }
1082 
alt_tse_select_pcs(struct phylink_config * config,phy_interface_t interface)1083 static struct phylink_pcs *alt_tse_select_pcs(struct phylink_config *config,
1084 					      phy_interface_t interface)
1085 {
1086 	struct net_device *ndev = to_net_dev(config->dev);
1087 	struct altera_tse_private *priv = netdev_priv(ndev);
1088 
1089 	if (interface == PHY_INTERFACE_MODE_SGMII ||
1090 	    interface == PHY_INTERFACE_MODE_1000BASEX)
1091 		return priv->pcs;
1092 	else
1093 		return NULL;
1094 }
1095 
1096 static const struct phylink_mac_ops alt_tse_phylink_ops = {
1097 	.mac_config = alt_tse_mac_config,
1098 	.mac_link_down = alt_tse_mac_link_down,
1099 	.mac_link_up = alt_tse_mac_link_up,
1100 	.mac_select_pcs = alt_tse_select_pcs,
1101 };
1102 
request_and_map(struct platform_device * pdev,const char * name,struct resource ** res,void __iomem ** ptr)1103 static int request_and_map(struct platform_device *pdev, const char *name,
1104 			   struct resource **res, void __iomem **ptr)
1105 {
1106 	struct device *device = &pdev->dev;
1107 	struct resource *region;
1108 
1109 	*res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
1110 	if (*res == NULL) {
1111 		dev_err(device, "resource %s not defined\n", name);
1112 		return -ENODEV;
1113 	}
1114 
1115 	region = devm_request_mem_region(device, (*res)->start,
1116 					 resource_size(*res), dev_name(device));
1117 	if (region == NULL) {
1118 		dev_err(device, "unable to request %s\n", name);
1119 		return -EBUSY;
1120 	}
1121 
1122 	*ptr = devm_ioremap(device, region->start,
1123 				    resource_size(region));
1124 	if (*ptr == NULL) {
1125 		dev_err(device, "ioremap of %s failed!", name);
1126 		return -ENOMEM;
1127 	}
1128 
1129 	return 0;
1130 }
1131 
1132 /* Probe Altera TSE MAC device
1133  */
altera_tse_probe(struct platform_device * pdev)1134 static int altera_tse_probe(struct platform_device *pdev)
1135 {
1136 	const struct of_device_id *of_id = NULL;
1137 	struct regmap_config pcs_regmap_cfg;
1138 	struct altera_tse_private *priv;
1139 	struct mdio_regmap_config mrc;
1140 	struct resource *control_port;
1141 	struct regmap *pcs_regmap;
1142 	struct resource *dma_res;
1143 	struct resource *pcs_res;
1144 	struct mii_bus *pcs_bus;
1145 	struct net_device *ndev;
1146 	void __iomem *descmap;
1147 	int ret = -ENODEV;
1148 
1149 	ndev = alloc_etherdev(sizeof(struct altera_tse_private));
1150 	if (!ndev) {
1151 		dev_err(&pdev->dev, "Could not allocate network device\n");
1152 		return -ENODEV;
1153 	}
1154 
1155 	SET_NETDEV_DEV(ndev, &pdev->dev);
1156 
1157 	priv = netdev_priv(ndev);
1158 	priv->device = &pdev->dev;
1159 	priv->dev = ndev;
1160 	priv->msg_enable = netif_msg_init(debug, default_msg_level);
1161 
1162 	of_id = of_match_device(altera_tse_ids, &pdev->dev);
1163 
1164 	if (of_id)
1165 		priv->dmaops = (struct altera_dmaops *)of_id->data;
1166 
1167 
1168 	if (priv->dmaops &&
1169 	    priv->dmaops->altera_dtype == ALTERA_DTYPE_SGDMA) {
1170 		/* Get the mapped address to the SGDMA descriptor memory */
1171 		ret = request_and_map(pdev, "s1", &dma_res, &descmap);
1172 		if (ret)
1173 			goto err_free_netdev;
1174 
1175 		/* Start of that memory is for transmit descriptors */
1176 		priv->tx_dma_desc = descmap;
1177 
1178 		/* First half is for tx descriptors, other half for tx */
1179 		priv->txdescmem = resource_size(dma_res)/2;
1180 
1181 		priv->txdescmem_busaddr = (dma_addr_t)dma_res->start;
1182 
1183 		priv->rx_dma_desc = (void __iomem *)((uintptr_t)(descmap +
1184 						     priv->txdescmem));
1185 		priv->rxdescmem = resource_size(dma_res)/2;
1186 		priv->rxdescmem_busaddr = dma_res->start;
1187 		priv->rxdescmem_busaddr += priv->txdescmem;
1188 
1189 		if (upper_32_bits(priv->rxdescmem_busaddr)) {
1190 			dev_dbg(priv->device,
1191 				"SGDMA bus addresses greater than 32-bits\n");
1192 			ret = -EINVAL;
1193 			goto err_free_netdev;
1194 		}
1195 		if (upper_32_bits(priv->txdescmem_busaddr)) {
1196 			dev_dbg(priv->device,
1197 				"SGDMA bus addresses greater than 32-bits\n");
1198 			ret = -EINVAL;
1199 			goto err_free_netdev;
1200 		}
1201 	} else if (priv->dmaops &&
1202 		   priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA) {
1203 		ret = request_and_map(pdev, "rx_resp", &dma_res,
1204 				      &priv->rx_dma_resp);
1205 		if (ret)
1206 			goto err_free_netdev;
1207 
1208 		ret = request_and_map(pdev, "tx_desc", &dma_res,
1209 				      &priv->tx_dma_desc);
1210 		if (ret)
1211 			goto err_free_netdev;
1212 
1213 		priv->txdescmem = resource_size(dma_res);
1214 		priv->txdescmem_busaddr = dma_res->start;
1215 
1216 		ret = request_and_map(pdev, "rx_desc", &dma_res,
1217 				      &priv->rx_dma_desc);
1218 		if (ret)
1219 			goto err_free_netdev;
1220 
1221 		priv->rxdescmem = resource_size(dma_res);
1222 		priv->rxdescmem_busaddr = dma_res->start;
1223 
1224 	} else {
1225 		ret = -ENODEV;
1226 		goto err_free_netdev;
1227 	}
1228 
1229 	if (!dma_set_mask(priv->device, DMA_BIT_MASK(priv->dmaops->dmamask))) {
1230 		dma_set_coherent_mask(priv->device,
1231 				      DMA_BIT_MASK(priv->dmaops->dmamask));
1232 	} else if (!dma_set_mask(priv->device, DMA_BIT_MASK(32))) {
1233 		dma_set_coherent_mask(priv->device, DMA_BIT_MASK(32));
1234 	} else {
1235 		ret = -EIO;
1236 		goto err_free_netdev;
1237 	}
1238 
1239 	/* MAC address space */
1240 	ret = request_and_map(pdev, "control_port", &control_port,
1241 			      (void __iomem **)&priv->mac_dev);
1242 	if (ret)
1243 		goto err_free_netdev;
1244 
1245 	/* xSGDMA Rx Dispatcher address space */
1246 	ret = request_and_map(pdev, "rx_csr", &dma_res,
1247 			      &priv->rx_dma_csr);
1248 	if (ret)
1249 		goto err_free_netdev;
1250 
1251 
1252 	/* xSGDMA Tx Dispatcher address space */
1253 	ret = request_and_map(pdev, "tx_csr", &dma_res,
1254 			      &priv->tx_dma_csr);
1255 	if (ret)
1256 		goto err_free_netdev;
1257 
1258 	memset(&pcs_regmap_cfg, 0, sizeof(pcs_regmap_cfg));
1259 	memset(&mrc, 0, sizeof(mrc));
1260 	/* SGMII PCS address space. The location can vary depending on how the
1261 	 * IP is integrated. We can have a resource dedicated to it at a specific
1262 	 * address space, but if it's not the case, we fallback to the mdiophy0
1263 	 * from the MAC's address space
1264 	 */
1265 	ret = request_and_map(pdev, "pcs", &pcs_res, &priv->pcs_base);
1266 	if (ret) {
1267 		/* If we can't find a dedicated resource for the PCS, fallback
1268 		 * to the internal PCS, that has a different address stride
1269 		 */
1270 		priv->pcs_base = priv->mac_dev + tse_csroffs(mdio_phy0);
1271 		pcs_regmap_cfg.reg_bits = 32;
1272 		/* Values are MDIO-like values, on 16 bits */
1273 		pcs_regmap_cfg.val_bits = 16;
1274 		pcs_regmap_cfg.reg_shift = REGMAP_UPSHIFT(2);
1275 	} else {
1276 		pcs_regmap_cfg.reg_bits = 16;
1277 		pcs_regmap_cfg.val_bits = 16;
1278 		pcs_regmap_cfg.reg_shift = REGMAP_UPSHIFT(1);
1279 	}
1280 
1281 	/* Create a regmap for the PCS so that it can be used by the PCS driver */
1282 	pcs_regmap = devm_regmap_init_mmio(&pdev->dev, priv->pcs_base,
1283 					   &pcs_regmap_cfg);
1284 	if (IS_ERR(pcs_regmap)) {
1285 		ret = PTR_ERR(pcs_regmap);
1286 		goto err_free_netdev;
1287 	}
1288 	mrc.regmap = pcs_regmap;
1289 	mrc.parent = &pdev->dev;
1290 	mrc.valid_addr = 0x0;
1291 	mrc.autoscan = false;
1292 
1293 	/* Rx IRQ */
1294 	priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq");
1295 	if (priv->rx_irq == -ENXIO) {
1296 		dev_err(&pdev->dev, "cannot obtain Rx IRQ\n");
1297 		ret = -ENXIO;
1298 		goto err_free_netdev;
1299 	}
1300 
1301 	/* Tx IRQ */
1302 	priv->tx_irq = platform_get_irq_byname(pdev, "tx_irq");
1303 	if (priv->tx_irq == -ENXIO) {
1304 		dev_err(&pdev->dev, "cannot obtain Tx IRQ\n");
1305 		ret = -ENXIO;
1306 		goto err_free_netdev;
1307 	}
1308 
1309 	/* get FIFO depths from device tree */
1310 	if (of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
1311 				 &priv->rx_fifo_depth)) {
1312 		dev_err(&pdev->dev, "cannot obtain rx-fifo-depth\n");
1313 		ret = -ENXIO;
1314 		goto err_free_netdev;
1315 	}
1316 
1317 	if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
1318 				 &priv->tx_fifo_depth)) {
1319 		dev_err(&pdev->dev, "cannot obtain tx-fifo-depth\n");
1320 		ret = -ENXIO;
1321 		goto err_free_netdev;
1322 	}
1323 
1324 	/* get hash filter settings for this instance */
1325 	priv->hash_filter =
1326 		of_property_read_bool(pdev->dev.of_node,
1327 				      "altr,has-hash-multicast-filter");
1328 
1329 	/* Set hash filter to not set for now until the
1330 	 * multicast filter receive issue is debugged
1331 	 */
1332 	priv->hash_filter = 0;
1333 
1334 	/* get supplemental address settings for this instance */
1335 	priv->added_unicast =
1336 		of_property_read_bool(pdev->dev.of_node,
1337 				      "altr,has-supplementary-unicast");
1338 
1339 	priv->dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN;
1340 	/* Max MTU is 1500, ETH_DATA_LEN */
1341 	priv->dev->max_mtu = ETH_DATA_LEN;
1342 
1343 	/* Get the max mtu from the device tree. Note that the
1344 	 * "max-frame-size" parameter is actually max mtu. Definition
1345 	 * in the ePAPR v1.1 spec and usage differ, so go with usage.
1346 	 */
1347 	of_property_read_u32(pdev->dev.of_node, "max-frame-size",
1348 			     &priv->dev->max_mtu);
1349 
1350 	/* The DMA buffer size already accounts for an alignment bias
1351 	 * to avoid unaligned access exceptions for the NIOS processor,
1352 	 */
1353 	priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE;
1354 
1355 	/* get default MAC address from device tree */
1356 	ret = of_get_ethdev_address(pdev->dev.of_node, ndev);
1357 	if (ret)
1358 		eth_hw_addr_random(ndev);
1359 
1360 	/* get phy addr and create mdio */
1361 	ret = altera_tse_phy_get_addr_mdio_create(ndev);
1362 
1363 	if (ret)
1364 		goto err_free_netdev;
1365 
1366 	/* initialize netdev */
1367 	ndev->mem_start = control_port->start;
1368 	ndev->mem_end = control_port->end;
1369 	ndev->netdev_ops = &altera_tse_netdev_ops;
1370 	altera_tse_set_ethtool_ops(ndev);
1371 
1372 	altera_tse_netdev_ops.ndo_set_rx_mode = tse_set_rx_mode;
1373 
1374 	if (priv->hash_filter)
1375 		altera_tse_netdev_ops.ndo_set_rx_mode =
1376 			tse_set_rx_mode_hashfilter;
1377 
1378 	/* Scatter/gather IO is not supported,
1379 	 * so it is turned off
1380 	 */
1381 	ndev->hw_features &= ~NETIF_F_SG;
1382 	ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1383 
1384 	/* VLAN offloading of tagging, stripping and filtering is not
1385 	 * supported by hardware, but driver will accommodate the
1386 	 * extra 4-byte VLAN tag for processing by upper layers
1387 	 */
1388 	ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1389 
1390 	/* setup NAPI interface */
1391 	netif_napi_add(ndev, &priv->napi, tse_poll);
1392 
1393 	spin_lock_init(&priv->mac_cfg_lock);
1394 	spin_lock_init(&priv->tx_lock);
1395 	spin_lock_init(&priv->rxdma_irq_lock);
1396 
1397 	netif_carrier_off(ndev);
1398 	ret = register_netdev(ndev);
1399 	if (ret) {
1400 		dev_err(&pdev->dev, "failed to register TSE net device\n");
1401 		goto err_register_netdev;
1402 	}
1403 
1404 	platform_set_drvdata(pdev, ndev);
1405 
1406 	priv->revision = ioread32(&priv->mac_dev->megacore_revision);
1407 
1408 	if (netif_msg_probe(priv))
1409 		dev_info(&pdev->dev, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n",
1410 			 (priv->revision >> 8) & 0xff,
1411 			 priv->revision & 0xff,
1412 			 (unsigned long) control_port->start, priv->rx_irq,
1413 			 priv->tx_irq);
1414 
1415 	snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-pcs-mii", ndev->name);
1416 	pcs_bus = devm_mdio_regmap_register(&pdev->dev, &mrc);
1417 	if (IS_ERR(pcs_bus)) {
1418 		ret = PTR_ERR(pcs_bus);
1419 		goto err_init_pcs;
1420 	}
1421 
1422 	priv->pcs = lynx_pcs_create_mdiodev(pcs_bus, 0);
1423 	if (IS_ERR(priv->pcs)) {
1424 		ret = PTR_ERR(priv->pcs);
1425 		goto err_init_pcs;
1426 	}
1427 
1428 	priv->phylink_config.dev = &ndev->dev;
1429 	priv->phylink_config.type = PHYLINK_NETDEV;
1430 	priv->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 |
1431 						MAC_100 | MAC_1000FD;
1432 
1433 	phy_interface_set_rgmii(priv->phylink_config.supported_interfaces);
1434 	__set_bit(PHY_INTERFACE_MODE_MII,
1435 		  priv->phylink_config.supported_interfaces);
1436 	__set_bit(PHY_INTERFACE_MODE_GMII,
1437 		  priv->phylink_config.supported_interfaces);
1438 	__set_bit(PHY_INTERFACE_MODE_SGMII,
1439 		  priv->phylink_config.supported_interfaces);
1440 	__set_bit(PHY_INTERFACE_MODE_1000BASEX,
1441 		  priv->phylink_config.supported_interfaces);
1442 
1443 	priv->phylink = phylink_create(&priv->phylink_config,
1444 				       of_fwnode_handle(priv->device->of_node),
1445 				       priv->phy_iface, &alt_tse_phylink_ops);
1446 	if (IS_ERR(priv->phylink)) {
1447 		dev_err(&pdev->dev, "failed to create phylink\n");
1448 		ret = PTR_ERR(priv->phylink);
1449 		goto err_init_phylink;
1450 	}
1451 
1452 	return 0;
1453 err_init_phylink:
1454 	lynx_pcs_destroy(priv->pcs);
1455 err_init_pcs:
1456 	unregister_netdev(ndev);
1457 err_register_netdev:
1458 	netif_napi_del(&priv->napi);
1459 	altera_tse_mdio_destroy(ndev);
1460 err_free_netdev:
1461 	free_netdev(ndev);
1462 	return ret;
1463 }
1464 
1465 /* Remove Altera TSE MAC device
1466  */
altera_tse_remove(struct platform_device * pdev)1467 static int altera_tse_remove(struct platform_device *pdev)
1468 {
1469 	struct net_device *ndev = platform_get_drvdata(pdev);
1470 	struct altera_tse_private *priv = netdev_priv(ndev);
1471 
1472 	platform_set_drvdata(pdev, NULL);
1473 	altera_tse_mdio_destroy(ndev);
1474 	unregister_netdev(ndev);
1475 	phylink_destroy(priv->phylink);
1476 	lynx_pcs_destroy(priv->pcs);
1477 
1478 	free_netdev(ndev);
1479 
1480 	return 0;
1481 }
1482 
1483 static const struct altera_dmaops altera_dtype_sgdma = {
1484 	.altera_dtype = ALTERA_DTYPE_SGDMA,
1485 	.dmamask = 32,
1486 	.reset_dma = sgdma_reset,
1487 	.enable_txirq = sgdma_enable_txirq,
1488 	.enable_rxirq = sgdma_enable_rxirq,
1489 	.disable_txirq = sgdma_disable_txirq,
1490 	.disable_rxirq = sgdma_disable_rxirq,
1491 	.clear_txirq = sgdma_clear_txirq,
1492 	.clear_rxirq = sgdma_clear_rxirq,
1493 	.tx_buffer = sgdma_tx_buffer,
1494 	.tx_completions = sgdma_tx_completions,
1495 	.add_rx_desc = sgdma_add_rx_desc,
1496 	.get_rx_status = sgdma_rx_status,
1497 	.init_dma = sgdma_initialize,
1498 	.uninit_dma = sgdma_uninitialize,
1499 	.start_rxdma = sgdma_start_rxdma,
1500 };
1501 
1502 static const struct altera_dmaops altera_dtype_msgdma = {
1503 	.altera_dtype = ALTERA_DTYPE_MSGDMA,
1504 	.dmamask = 64,
1505 	.reset_dma = msgdma_reset,
1506 	.enable_txirq = msgdma_enable_txirq,
1507 	.enable_rxirq = msgdma_enable_rxirq,
1508 	.disable_txirq = msgdma_disable_txirq,
1509 	.disable_rxirq = msgdma_disable_rxirq,
1510 	.clear_txirq = msgdma_clear_txirq,
1511 	.clear_rxirq = msgdma_clear_rxirq,
1512 	.tx_buffer = msgdma_tx_buffer,
1513 	.tx_completions = msgdma_tx_completions,
1514 	.add_rx_desc = msgdma_add_rx_desc,
1515 	.get_rx_status = msgdma_rx_status,
1516 	.init_dma = msgdma_initialize,
1517 	.uninit_dma = msgdma_uninitialize,
1518 	.start_rxdma = msgdma_start_rxdma,
1519 };
1520 
1521 static const struct of_device_id altera_tse_ids[] = {
1522 	{ .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, },
1523 	{ .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, },
1524 	{ .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, },
1525 	{},
1526 };
1527 MODULE_DEVICE_TABLE(of, altera_tse_ids);
1528 
1529 static struct platform_driver altera_tse_driver = {
1530 	.probe		= altera_tse_probe,
1531 	.remove		= altera_tse_remove,
1532 	.suspend	= NULL,
1533 	.resume		= NULL,
1534 	.driver		= {
1535 		.name	= ALTERA_TSE_RESOURCE_NAME,
1536 		.of_match_table = altera_tse_ids,
1537 	},
1538 };
1539 
1540 module_platform_driver(altera_tse_driver);
1541 
1542 MODULE_AUTHOR("Altera Corporation");
1543 MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver");
1544 MODULE_LICENSE("GPL v2");
1545