ethernet/cadence/macb.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  * Copyright (C) 2004-2006 Atmel Corporation
32 #define MACB_RBQP		0x0018 /* RX Q Base Address */
85 #define GEM_PBUFRXCUT		0x0044 /* RX Partial Store and Forward */
99 #define GEM_RXPTPUNI		0x00D4 /* PTP RX Unicast address */
113 #define GEM_TX65CNT		0x011c /* 65-127 byte Frames TX counter */
114 #define GEM_TX128CNT		0x0120 /* 128-255 byte Frames TX counter */
115 #define GEM_TX256CNT		0x0124 /* 256-511 byte Frames TX counter */
116 #define GEM_TX512CNT		0x0128 /* 512-1023 byte Frames TX counter */
117 #define GEM_TX1024CNT		0x012c /* 1024-1518 byte Frames TX counter */
133 #define GEM_RX64CNT		0x0168 /* 64 byte Frames RX Counter */
134 #define GEM_RX65CNT		0x016c /* 65-127 byte Frames RX Counter */
135 #define GEM_RX128CNT		0x0170 /* 128-255 byte Frames RX Counter */
136 #define GEM_RX256CNT		0x0174 /* 256-511 byte Frames RX Counter */
137 #define GEM_RX512CNT		0x0178 /* 512-1023 byte Frames RX Counter */
138 #define GEM_RX1024CNT		0x017c /* 1024-1518 byte Frames RX Counter */
139 #define GEM_RX1519CNT		0x0180 /* 1519+ byte Frames RX Counter */
152 #define GEM_TISUBN		0x01bc /* 1588 Timer Increment Sub-ns */
160 #define GEM_EFRSL		0x01e8 /* PTP Event Frame Rx Seconds Low */
161 #define GEM_EFRN		0x01ec /* PTP Event Frame Rx Nanoseconds */
164 #define GEM_PEFRSL		0x01f8 /* PTP Peer Event Frame Rx Sec Low */
165 #define GEM_PEFRN		0x01fc /* PTP Peer Event Frame Rx Ns */
166 #define GEM_PCSCNTRL		0x0200 /* PCS Control */
167 #define GEM_PCSSTS		0x0204 /* PCS Status */
168 #define GEM_PCSPHYTOPID		0x0208 /* PCS PHY Top ID */
169 #define GEM_PCSPHYBOTID		0x020c /* PCS PHY Bottom ID */
170 #define GEM_PCSANADV		0x0210 /* PCS AN Advertisement */
171 #define GEM_PCSANLPBASE		0x0214 /* PCS AN Link Partner Base */
172 #define GEM_PCSANEXP		0x0218 /* PCS AN Expansion */
173 #define GEM_PCSANNPTX		0x021c /* PCS AN Next Page TX */
174 #define GEM_PCSANNPLP		0x0220 /* PCS AN Next Page LP */
175 #define GEM_PCSANEXTSTS		0x023c /* PCS AN Extended Status */
186 #define GEM_USX_CONTROL		0x0A80 /* High speed PCS control register */
187 #define GEM_USX_STATUS		0x0A88 /* High speed PCS status register */
190 #define GEM_RXBDCTRL	0x04d0 /* RX Buffer Descriptor control register */
210 /* Which screening type 2 EtherType register will be used (0 - 7) */
263 #define MACB_BIT_RATE_OFFSET	2 /* Discard non-VLAN frames */
333 #define GEM_RXBMS_OFFSET	8 /* RX packet buffer memory size select */
343 #define GEM_RXEXT_OFFSET	28 /* RX extended Buffer Descriptor mode */
347 #define GEM_ADDR64_OFFSET	30 /* Address bus width - 64b or 32b */
352 #define GEM_ENCUTTHRU_OFFSET	31 /* Enable RX partial store and forward */
394 #define MACB_RXUBR_OFFSET	2 /* RX used bit read */
418 #define MACB_WOL_OFFSET		14 /* Enable wake-on-lan interrupt */
438 #define GEM_WOL_OFFSET		28 /* Enable wake-on-lan interrupt */
603 #define GEM_RXTSMODE_OFFSET			4 /* RX Descriptor Timestamp Insertion mode */
617 #define GEM_CMPA_OFFSET				13 /* Compare A - Index to screener type 2 Compare register */
621 #define GEM_CMPB_OFFSET				19 /* Compare B - Index to screener type 2 Compare register */
625 #define GEM_CMPC_OFFSET				25 /* Compare C - Index to screener type 2 Compare register */
690 #define GEM_DMA_SEC_MASK			(GEM_DMA_SEC_TOP - 1)
753 	(((value) & ((1 << MACB_##name##_SIZE) - 1))	\
757 	 & ((1 << MACB_##name##_SIZE) - 1))
759 	(((old) & ~(((1 << MACB_##name##_SIZE) - 1)	\
766 	(((value) & ((1 << GEM_##name##_SIZE) - 1))	\
770 	 & ((1 << GEM_##name##_SIZE) - 1))
772 	(((old) & ~(((1 << GEM_##name##_SIZE) - 1)	\
777 #define macb_readl(port, reg)		(port)->macb_reg_readl((port), MACB_##reg)
778 #define macb_writel(port, reg, value)	(port)->macb_reg_writel((port), MACB_##reg, (value))
779 #define gem_readl(port, reg)		(port)->macb_reg_readl((port), GEM_##reg)
780 #define gem_writel(port, reg, value)	(port)->macb_reg_writel((port), GEM_##reg, (value))
781 #define queue_readl(queue, reg)		(queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
782 #define queue_writel(queue, reg, value)	(queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (va…
783 #define gem_readl_n(port, reg, idx)		(port)->macb_reg_readl((port), GEM_##reg + idx * 4)
784 #define gem_writel_n(port, reg, idx, value)	(port)->macb_reg_writel((port), GEM_##reg + idx * 4, (v…
811 /* struct macb_dma_desc - Hardware DMA descriptor
883 /* RX checksum offload disabled: bit 24 clear in NCFGR */
887 /* RX checksum offload enabled: bit 24 set in NCFGR */
923 /* limit RX checksum offload to TCP and UDP packets */
929 /* struct macb_tx_skb - data about an skb which is being transmitted
944 /* Hardware-collected statistics. Used when updating the network
1020  * returned by `ethtool -S`. Also describes which net_device_stats statistics
1159 /* MACB-PTP interface: adapt to platform needs. */
1304 	/* holds value of rx watermark value for pbuf_rxcutthru register */
1307 	struct macb_ptp_info	*ptp_info;	/* macb-ptp interface */
1321 	/* RX queue filer rule set*/
1339 #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
1340 #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
1355 	if (bp->tstamp_config.tx_type == TSTAMP_DISABLED)  in gem_ptp_do_txstamp()
1363 	if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED)  in gem_ptp_do_rxstamp()
1380 	return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);  in macb_is_gem()
1385 	return IS_ENABLED(CONFIG_MACB_USE_HWSTAMP) && (bp->caps & MACB_CAPS_GEM_HAS_PTP);  in gem_has_ptp()
1389  * struct macb_platform_data - platform data for MACB Ethernet used for PCI registration