Home
last modified time | relevance | path

Searched +full:rst +full:- +full:mgr (Results 1 – 25 of 37) sorted by relevance

12

/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Daltr,rst-mgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/altr,rst-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <dinguyen@kernel.org>
15 - description: Cyclone5/Arria5/Arria10
16 const: altr,rst-mgr
17 - description: Stratix10 ARM64 SoC
19 - const: altr,stratix10-rst-mgr
20 - const: altr,rst-mgr
[all …]
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "altr,socfpga-stratix10";
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53", "arm,armv8";
[all …]
H A Dsocfpga_arria10.dtsi17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 tick-timer = &timer2;
26 u-boot,dm-pre-reloc;
30 #address-cells = <1>;
31 #size-cells = <0>;
32 enable-method = "altr,socfpga-a10-smp";
35 compatible = "arm,cortex-a9";
[all …]
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
[all …]
/openbmc/u-boot/doc/device-tree-bindings/fpga/
H A Daltera-socfpga-a10-fpga-mgr.txt4 - compatible : should contain "altr,socfpga-a10-fpga-mgr"
5 - reg : base address and size for memory mapped io.
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
8 - resets : Phandle and reset specifier for the device's reset.
9 - clocks : Clocks used by the device.
13 fpga_mgr: fpga-mgr@ffd03000 {
14 compatible = "altr,socfpga-a10-fpga-mgr";
18 resets = <&rst FPGAMGR_RESET>;
/openbmc/linux/Documentation/devicetree/bindings/fpga/
H A Daltera-socfpga-a10-fpga-mgr.txt4 - compatible : should contain "altr,socfpga-a10-fpga-mgr"
5 - reg : base address and size for memory mapped io.
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
8 - resets : Phandle and reset specifier for the device's reset.
9 - clocks : Clocks used by the device.
13 fpga_mgr: fpga-mgr@ffd03000 {
14 compatible = "altr,socfpga-a10-fpga-mgr";
18 resets = <&rst FPGAMGR_RESET>;
H A Dfpga-region.txt6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
82 ---------------- ----------------------------------
85 | ----| | ----------- -------- |
87 | | W | | | ----------- -------- |
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
[all …]
/openbmc/linux/drivers/reset/
H A Dreset-socfpga.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copied from reset-sunxi.c
13 #include <linux/reset-controller.h>
14 #include <linux/reset/reset-simple.h>
32 return -ENOMEM; in a10_reset_init()
39 if (!request_mem_region(res.start, size, np->name)) { in a10_reset_init()
40 ret = -EBUSY; in a10_reset_init()
44 data->membase = ioremap(res.start, size); in a10_reset_init()
45 if (!data->membase) { in a10_reset_init()
46 ret = -ENOMEM; in a10_reset_init()
[all …]
H A Dreset-a10sr.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Adapted from reset-socfpga.c
11 #include <linux/mfd/altera-a10sr.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/reset/altr,rst-mgr-a10sr.h>
40 return -EINVAL; in a10sr_reset_shift()
52 return regmap_update_bits(a10r->regmap, index, mask, assert ? 0 : mask); in a10sr_reset_update()
77 ret = regmap_read(a10r->regmap, index, &value); in a10sr_reset_status()
92 struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent); in a10sr_reset_probe()
95 a10r = devm_kzalloc(&pdev->dev, sizeof(struct a10sr_reset), in a10sr_reset_probe()
[all …]
/openbmc/linux/arch/arm/mach-socfpga/
H A Dsocfpga.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012-2015 Altera Corporation
26 np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr"); in socfpga_sysmgr_init()
28 if (of_property_read_u32(np, "cpu1-start-addr", in socfpga_sysmgr_init()
30 pr_err("SMP: Need cpu1-start-addr in device tree.\n"); in socfpga_sysmgr_init()
38 np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); in socfpga_sysmgr_init()
41 np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl"); in socfpga_sysmgr_init()
108 "altr,socfpga-arria10",
/openbmc/linux/include/dt-bindings/reset/
H A Daltr,rst-mgr-a10sr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Adapted from altr,rst-mgr-a10.h
H A Daltr,rst-mgr-s10.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
71 /* 82-87 is empty */
90 /* 164-167 is empty */
/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dbosch,c_can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Dario Binacchi <dariobin@libero.it>
15 - $ref: can-controller.yaml#
20 - enum:
21 - bosch,c_can
22 - bosch,d_can
23 - ti,dra7-d_can
24 - ti,am3352-d_can
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dreset_manager_gen5.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
9 #include <dt-bindings/reset/altr,rst-mgr.h>
H A Dreset_manager_arria10.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2016-2017 Intel Corporation
9 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
/openbmc/u-boot/include/dt-bindings/reset/
H A Daltr,rst-mgr-s10.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2016-2018 Intel Corporation. All rights reserved
5 * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
65 /* 77-79 is empty */
68 /* 82-87 is empty */
86 /* 164-167 is empty */
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dreset_manager_s10.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
11 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
20 /* Assert or de-assert SoCFPGA reset manager reset. */
26 reg = &reset_manager_base->mpumodrst; in socfpga_per_reset()
28 reg = &reset_manager_base->per0modrst; in socfpga_per_reset()
30 reg = &reset_manager_base->per1modrst; in socfpga_per_reset()
32 reg = &reset_manager_base->brgmodrst; in socfpga_per_reset()
53 &reset_manager_base->per0modrst); in socfpga_per_reset_all()
54 writel(~l4wd0, &reset_manager_base->per0modrst); in socfpga_per_reset_all()
[all …]
H A Dmisc_s10.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
20 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
37 -1,
57 return -EINVAL; in socfpga_phymode_setup()
67 return -EINVAL; in socfpga_phymode_setup()
69 clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index, in socfpga_phymode_setup()
78 const void *fdt = gd->fdt_blob; in socfpga_set_phymode()
95 "#reset-cells", 1, 0, in socfpga_set_phymode()
102 gmac_index = args.args[0] - EMAC0_RESET; in socfpga_set_phymode()
[all …]
/openbmc/u-boot/drivers/reset/
H A Dreset-socfpga.c1 // SPDX-License-Identifier: GPL-2.0+
12 * Maxime Ripard <maxime.ripard@free-electrons.com>
18 #include <reset-uclass.h>
32 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); in socfpga_reset_assert()
33 int id = reset_ctl->id; in socfpga_reset_assert()
38 setbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset)); in socfpga_reset_assert()
44 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); in socfpga_reset_deassert()
45 int id = reset_ctl->id; in socfpga_reset_deassert()
50 clrbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset)); in socfpga_reset_deassert()
57 reset_ctl, reset_ctl->dev, reset_ctl->id); in socfpga_reset_request()
[all …]
/openbmc/docs/designs/
H A Dentity-manager-hw-id-vpd-discover-via-device-tree.md1 # Entity-Manager HW ID: VPD Discovery via Device-Tree Properties
12 data via non-I2C channels and in a proprietary format that is not covered by
13 Entity-Manager's 'fru-device' daemon that most platforms rely on.
16 gathered from device tree file paths for Entity-Manager consumption.
20 Typical platforms provide HW ID data - often referred to as 'vital product data'
21 (VPD) - for the baseboard as a FRU storage blob held in a physical EEPROM.
23 [As described in Entity-Manager documentation](https://github.com/openbmc/entity-manager/blob/maste…
25 copied to D-Bus as properties of the `xyz.openbmc_project.FruDevice` interface
26 by Entity-Manager's fru-device daemon. The current FRU-device daemon is able to
27 decode IPMI-FRU storage formatted blobs, as well as the Tyan data format.
[all …]

12