19952f691SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2843fc75aSThor Thayer /* 3843fc75aSThor Thayer * Copyright Intel Corporation (C) 2017. All Rights Reserved 4843fc75aSThor Thayer * 5843fc75aSThor Thayer * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip 6843fc75aSThor Thayer * 7843fc75aSThor Thayer * Adapted from altr,rst-mgr-a10.h 8843fc75aSThor Thayer */ 9843fc75aSThor Thayer 10843fc75aSThor Thayer #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H 11843fc75aSThor Thayer #define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H 12843fc75aSThor Thayer 13843fc75aSThor Thayer /* Peripheral PHY resets */ 14843fc75aSThor Thayer #define A10SR_RESET_ENET_HPS 0 15843fc75aSThor Thayer #define A10SR_RESET_PCIE 1 16843fc75aSThor Thayer #define A10SR_RESET_FILE 2 17843fc75aSThor Thayer #define A10SR_RESET_BQSPI 3 18843fc75aSThor Thayer #define A10SR_RESET_USB 4 19843fc75aSThor Thayer 20843fc75aSThor Thayer #define A10SR_RESET_NUM 5 21843fc75aSThor Thayer 22843fc75aSThor Thayer #endif 23