1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 22b09ea48SLey Foon Tan /* 32b09ea48SLey Foon Tan * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 42b09ea48SLey Foon Tan */ 52b09ea48SLey Foon Tan 62b09ea48SLey Foon Tan #ifndef _RESET_MANAGER_GEN5_H_ 72b09ea48SLey Foon Tan #define _RESET_MANAGER_GEN5_H_ 82b09ea48SLey Foon Tan 92b09ea48SLey Foon Tan #include <dt-bindings/reset/altr,rst-mgr.h> 102b09ea48SLey Foon Tan 112b09ea48SLey Foon Tan void reset_deassert_peripherals_handoff(void); 122b09ea48SLey Foon Tan void socfpga_bridges_reset(int enable); 132b09ea48SLey Foon Tan 142b09ea48SLey Foon Tan struct socfpga_reset_manager { 152b09ea48SLey Foon Tan u32 status; 162b09ea48SLey Foon Tan u32 ctrl; 172b09ea48SLey Foon Tan u32 counts; 182b09ea48SLey Foon Tan u32 padding1; 192b09ea48SLey Foon Tan u32 mpu_mod_reset; 202b09ea48SLey Foon Tan u32 per_mod_reset; 212b09ea48SLey Foon Tan u32 per2_mod_reset; 222b09ea48SLey Foon Tan u32 brg_mod_reset; 232b09ea48SLey Foon Tan u32 misc_mod_reset; 242b09ea48SLey Foon Tan u32 padding2[12]; 252b09ea48SLey Foon Tan u32 tstscratch; 262b09ea48SLey Foon Tan }; 272b09ea48SLey Foon Tan 282b09ea48SLey Foon Tan /* 292b09ea48SLey Foon Tan * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: 302b09ea48SLey Foon Tan * 0 ... mpumodrst 312b09ea48SLey Foon Tan * 1 ... permodrst 322b09ea48SLey Foon Tan * 2 ... per2modrst 332b09ea48SLey Foon Tan * 3 ... brgmodrst 342b09ea48SLey Foon Tan * 4 ... miscmodrst 352b09ea48SLey Foon Tan */ 362b09ea48SLey Foon Tan #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) 372b09ea48SLey Foon Tan #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) 382b09ea48SLey Foon Tan #define RSTMGR_NAND RSTMGR_DEFINE(1, 4) 392b09ea48SLey Foon Tan #define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) 402b09ea48SLey Foon Tan #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) 412b09ea48SLey Foon Tan #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) 422b09ea48SLey Foon Tan #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) 432b09ea48SLey Foon Tan #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) 442b09ea48SLey Foon Tan #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) 452b09ea48SLey Foon Tan #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) 462b09ea48SLey Foon Tan #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) 472b09ea48SLey Foon Tan #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) 482b09ea48SLey Foon Tan 492b09ea48SLey Foon Tan #endif /* _RESET_MANAGER_GEN5_H_ */ 50