Home
last modified time | relevance | path

Searched +full:rockchip +full:- +full:pcie +full:- +full:phy (Results 1 – 25 of 61) sorted by relevance

123

/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-naneng-combphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC Naneng Combo Phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3588-naneng-combphy
23 - description: reference clock
24 - description: apb clock
[all …]
H A Drockchip-pcie-phy.txt1 Rockchip PCIE PHY
2 -----------------------
5 - compatible: rockchip,rk3399-pcie-phy
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
11 - reset-names: Must be "phy"
13 Required properties for legacy PHY mode (deprecated):
14 - #phy-cells: must be 0
[all …]
H A Drockchip,pcie3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip PCIe v3 phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-pcie3-phy
16 - rockchip,rk3588-pcie3-phy
25 clock-names:
29 data-lanes:
[all …]
/openbmc/linux/drivers/phy/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
19 associated to the Rockchip ISP module present in RK3399 SoCs.
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
[all …]
H A Dphy-rockchip-snps-pcie3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PCIE3.0 phy driver
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
58 struct phy *phy; member
69 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) in rockchip_p3phy_set_mode() argument
71 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rockchip_p3phy_set_mode()
76 priv->mode = PHY_MODE_PCIE_RC; in rockchip_p3phy_set_mode()
79 priv->mode = PHY_MODE_PCIE_EP; in rockchip_p3phy_set_mode()
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
3 obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX0) += phy-rockchip-dphy-rx0.o
4 obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
5 obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o
6 obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
7 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
8 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
9 obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
10 obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
[all …]
H A Dphy-rockchip-pcie.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip PCIe PHY driver
5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
6 * Copyright (C) 2016 ROCKCHIP, Inc.
17 #include <linux/phy/phy.h>
23 * The higher 16-bit of this register is used for write protection
69 struct phy *phy; member
82 phys[inst->index]); in to_pcie_phy()
85 static struct phy *rockchip_pcie_phy_of_xlate(struct device *dev, in rockchip_pcie_phy_of_xlate()
90 if (args->args_count == 0) in rockchip_pcie_phy_of_xlate()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Drockchip,rk3399-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Endpoint
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-ep.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie-ep
22 reg-names:
[all …]
H A Drockchip-dw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
16 PCIe IP and thus inherits all the common properties defined in
[all …]
H A Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Root Port Bridge Host
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
[all …]
H A Drockchip,rk3399-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Bridge Common Properties
10 - Shawn Lin <shawn.lin@rock-chips.com>
19 clock-names:
21 - const: aclk
22 - const: aclk-perf
23 - const: hclk
[all …]
/openbmc/linux/drivers/pci/controller/dwc/
H A Dpcie-dw-rockchip.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Rockchip SoCs.
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 * http://www.rock-chips.com
8 * Author: Simon Xue <xxm@rock-chips.com>
19 #include <linux/phy/phy.h>
24 #include "pcie-designware.h"
34 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
54 struct phy *phy; member
63 static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, in rockchip_pcie_readl_apb() argument
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
7 #include "rk3588-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
16 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
21 compatible = "rockchip,rk3588-i2s-tdm";
25 clock-names = "mclk_tx", "mclk_rx", "hclk";
26 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
27 assigned-clock-parents = <&cru PLL_AUPLL>;
29 dma-names = "tx";
[all …]
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
9 compatible = "rockchip,rk3568";
12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
16 clock-names = "sata", "pmalive", "rxoob";
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568_PD_PIPE>;
26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
31 compatible = "rockchip,rk3568-qos", "syscon";
[all …]
H A Drk3568-lubancat-2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
17 compatible = "embedfire,lubancat-2", "rockchip,rk3568";
27 stdout-path = "serial2:1500000n8";
31 compatible = "gpio-leds";
[all …]
H A Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3399";
[all …]
H A Drk3568-rock-3a.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
12 compatible = "radxa,rock3a", "rockchip,rk3568";
21 stdout-path = "serial2:1500000n8";
24 hdmi-con {
25 compatible = "hdmi-connector";
[all …]
H A Drk3568-radxa-e25.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include "rk3568-radxa-cm3i.dtsi"
8 compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
14 pwm-leds {
15 compatible = "pwm-leds-multicolor";
17 multi-led {
19 max-brightness = <255>;
21 led-red {
26 led-green {
[all …]
H A Drk3399-ficus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
9 /dts-v1/;
10 #include "rk3399-rock960.dtsi"
14 compatible = "vamrs,ficus", "rockchip,rk3399";
17 stdout-path = "serial2:1500000n8";
20 clkin_gmac: external-gmac-clock {
21 compatible = "fixed-clock";
22 clock-frequency = <125000000>;
23 clock-output-names = "clkin_gmac";
[all …]
H A Drk3568-roc-pc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/soc/rockchip,vop2.h>
15 compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568";
25 stdout-path = "serial2:1500000n8";
28 dc_12v: dc-12v-regulator {
29 compatible = "regulator-fixed";
[all …]
H A Drk3568-odroid-m1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,vop2.h>
15 model = "Hardkernel ODROID-M1";
16 compatible = "hardkernel,odroid-m1", "rockchip,rk3568";
29 stdout-path = "serial2:1500000n8";
32 dc_12v: dc-12v-regulator {
[all …]
/openbmc/linux/drivers/pci/controller/
H A Dpcie-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe host controller driver
5 * Copyright (c) 2016 Rockchip, Inc.
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
20 #include <linux/phy/phy.h>
25 #include "pcie-rockchip.h"
27 int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) in rockchip_pcie_parse_dt() argument
29 struct device *dev = rockchip->dev; in rockchip_pcie_parse_dt()
31 struct device_node *node = dev->of_node; in rockchip_pcie_parse_dt()
[all …]
H A Dpcie-rockchip-host.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe host controller driver
5 * Copyright (c) 2016 Rockchip, Inc.
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
31 #include <linux/phy/phy.h>
37 #include "pcie-rockchip.h"
39 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip) in rockchip_pcie_enable_bw_int() argument
43 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); in rockchip_pcie_enable_bw_int()
45 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); in rockchip_pcie_enable_bw_int()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/rockchip/grf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip General Register Files (GRF)
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-ficus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
9 /dts-v1/;
10 #include "rk3399-rock960.dtsi"
11 #include "rk3399-sdram-ddr3-1600.dtsi"
15 compatible = "vamrs,ficus", "rockchip,rk3399";
18 stdout-path = "serial2:1500000n8";
21 clkin_gmac: external-gmac-clock {
22 compatible = "fixed-clock";
23 clock-frequency = <125000000>;
[all …]

123