1b11c8215SShawn LinRockchip PCIE PHY 2b11c8215SShawn Lin----------------------- 3b11c8215SShawn Lin 4b11c8215SShawn LinRequired properties: 5b11c8215SShawn Lin - compatible: rockchip,rk3399-pcie-phy 6b11c8215SShawn Lin - clocks: Must contain an entry in clock-names. 7b11c8215SShawn Lin See ../clocks/clock-bindings.txt for details. 8b11c8215SShawn Lin - clock-names: Must be "refclk" 9b11c8215SShawn Lin - resets: Must contain an entry in reset-names. 10b11c8215SShawn Lin See ../reset/reset.txt for details. 11b11c8215SShawn Lin - reset-names: Must be "phy" 12b11c8215SShawn Lin 1305b57273SShawn LinRequired properties for legacy PHY mode (deprecated): 1405b57273SShawn Lin - #phy-cells: must be 0 1505b57273SShawn Lin 1605b57273SShawn LinRequired properties for per-lane PHY mode (preferred): 1705b57273SShawn Lin - #phy-cells: must be 1 1805b57273SShawn Lin 19b11c8215SShawn LinExample: 20b11c8215SShawn Lin 21b11c8215SShawn Lingrf: syscon@ff770000 { 22b11c8215SShawn Lin compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 23b11c8215SShawn Lin #address-cells = <1>; 24b11c8215SShawn Lin #size-cells = <1>; 25b11c8215SShawn Lin 26b11c8215SShawn Lin ... 27b11c8215SShawn Lin 28b11c8215SShawn Lin pcie_phy: pcie-phy { 29b11c8215SShawn Lin compatible = "rockchip,rk3399-pcie-phy"; 30b11c8215SShawn Lin #phy-cells = <0>; 31b11c8215SShawn Lin clocks = <&cru SCLK_PCIEPHY_REF>; 32b11c8215SShawn Lin clock-names = "refclk"; 33b11c8215SShawn Lin resets = <&cru SRST_PCIEPHY>; 34b11c8215SShawn Lin reset-names = "phy"; 35b11c8215SShawn Lin }; 36b11c8215SShawn Lin}; 37