175be98eeSFrank Wunderlich# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 275be98eeSFrank Wunderlich%YAML 1.2 375be98eeSFrank Wunderlich--- 475be98eeSFrank Wunderlich$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml# 575be98eeSFrank Wunderlich$schema: http://devicetree.org/meta-schemas/core.yaml# 675be98eeSFrank Wunderlich 775be98eeSFrank Wunderlichtitle: Rockchip PCIe v3 phy 875be98eeSFrank Wunderlich 975be98eeSFrank Wunderlichmaintainers: 1075be98eeSFrank Wunderlich - Heiko Stuebner <heiko@sntech.de> 1175be98eeSFrank Wunderlich 1275be98eeSFrank Wunderlichproperties: 1375be98eeSFrank Wunderlich compatible: 1475be98eeSFrank Wunderlich enum: 1575be98eeSFrank Wunderlich - rockchip,rk3568-pcie3-phy 16*f66782cfSSebastian Reichel - rockchip,rk3588-pcie3-phy 1775be98eeSFrank Wunderlich 1875be98eeSFrank Wunderlich reg: 1975be98eeSFrank Wunderlich maxItems: 1 2075be98eeSFrank Wunderlich 2175be98eeSFrank Wunderlich clocks: 22*f66782cfSSebastian Reichel minItems: 1 2375be98eeSFrank Wunderlich maxItems: 3 2475be98eeSFrank Wunderlich 2575be98eeSFrank Wunderlich clock-names: 26*f66782cfSSebastian Reichel minItems: 1 27*f66782cfSSebastian Reichel maxItems: 3 2875be98eeSFrank Wunderlich 2975be98eeSFrank Wunderlich data-lanes: 3075be98eeSFrank Wunderlich description: which lanes (by position) should be mapped to which 3175be98eeSFrank Wunderlich controller (value). 0 means lane disabled, higher value means used. 3275be98eeSFrank Wunderlich (controller-number +1 ) 3375be98eeSFrank Wunderlich $ref: /schemas/types.yaml#/definitions/uint32-array 3475be98eeSFrank Wunderlich minItems: 2 3575be98eeSFrank Wunderlich maxItems: 16 3675be98eeSFrank Wunderlich items: 3775be98eeSFrank Wunderlich minimum: 0 3875be98eeSFrank Wunderlich maximum: 16 3975be98eeSFrank Wunderlich 4075be98eeSFrank Wunderlich "#phy-cells": 4175be98eeSFrank Wunderlich const: 0 4275be98eeSFrank Wunderlich 4375be98eeSFrank Wunderlich resets: 4475be98eeSFrank Wunderlich maxItems: 1 4575be98eeSFrank Wunderlich 4675be98eeSFrank Wunderlich reset-names: 4775be98eeSFrank Wunderlich const: phy 4875be98eeSFrank Wunderlich 4975be98eeSFrank Wunderlich rockchip,phy-grf: 5075be98eeSFrank Wunderlich $ref: /schemas/types.yaml#/definitions/phandle 5175be98eeSFrank Wunderlich description: phandle to the syscon managing the phy "general register files" 5275be98eeSFrank Wunderlich 5375be98eeSFrank Wunderlich rockchip,pipe-grf: 5475be98eeSFrank Wunderlich $ref: /schemas/types.yaml#/definitions/phandle 5575be98eeSFrank Wunderlich description: phandle to the syscon managing the pipe "general register files" 5675be98eeSFrank Wunderlich 5775be98eeSFrank Wunderlichrequired: 5875be98eeSFrank Wunderlich - compatible 5975be98eeSFrank Wunderlich - reg 6075be98eeSFrank Wunderlich - rockchip,phy-grf 6175be98eeSFrank Wunderlich - "#phy-cells" 6275be98eeSFrank Wunderlich 63*f66782cfSSebastian ReichelallOf: 64*f66782cfSSebastian Reichel - if: 65*f66782cfSSebastian Reichel properties: 66*f66782cfSSebastian Reichel compatible: 67*f66782cfSSebastian Reichel enum: 68*f66782cfSSebastian Reichel - rockchip,rk3588-pcie3-phy 69*f66782cfSSebastian Reichel then: 70*f66782cfSSebastian Reichel properties: 71*f66782cfSSebastian Reichel clocks: 72*f66782cfSSebastian Reichel maxItems: 1 73*f66782cfSSebastian Reichel clock-names: 74*f66782cfSSebastian Reichel items: 75*f66782cfSSebastian Reichel - const: pclk 76*f66782cfSSebastian Reichel else: 77*f66782cfSSebastian Reichel properties: 78*f66782cfSSebastian Reichel clocks: 79*f66782cfSSebastian Reichel minItems: 3 80*f66782cfSSebastian Reichel 81*f66782cfSSebastian Reichel clock-names: 82*f66782cfSSebastian Reichel items: 83*f66782cfSSebastian Reichel - const: refclk_m 84*f66782cfSSebastian Reichel - const: refclk_n 85*f66782cfSSebastian Reichel - const: pclk 86*f66782cfSSebastian Reichel 8775be98eeSFrank WunderlichadditionalProperties: false 8875be98eeSFrank Wunderlich 8975be98eeSFrank Wunderlichexamples: 9075be98eeSFrank Wunderlich - | 9175be98eeSFrank Wunderlich #include <dt-bindings/clock/rk3568-cru.h> 9275be98eeSFrank Wunderlich pcie30phy: phy@fe8c0000 { 9375be98eeSFrank Wunderlich compatible = "rockchip,rk3568-pcie3-phy"; 9475be98eeSFrank Wunderlich reg = <0xfe8c0000 0x20000>; 9575be98eeSFrank Wunderlich #phy-cells = <0>; 9675be98eeSFrank Wunderlich clocks = <&pmucru CLK_PCIE30PHY_REF_M>, 9775be98eeSFrank Wunderlich <&pmucru CLK_PCIE30PHY_REF_N>, 9875be98eeSFrank Wunderlich <&cru PCLK_PCIE30PHY>; 9975be98eeSFrank Wunderlich clock-names = "refclk_m", "refclk_n", "pclk"; 10075be98eeSFrank Wunderlich resets = <&cru SRST_PCIE30PHY>; 10175be98eeSFrank Wunderlich reset-names = "phy"; 10275be98eeSFrank Wunderlich rockchip,phy-grf = <&pcie30_phy_grf>; 10375be98eeSFrank Wunderlich }; 104