1fd358326SDongjin Kim// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2fd358326SDongjin Kim/*
3fd358326SDongjin Kim * Copyright (c) 2022 Hardkernel Co., Ltd.
4fd358326SDongjin Kim *
5fd358326SDongjin Kim */
6fd358326SDongjin Kim
7fd358326SDongjin Kim/dts-v1/;
8fd358326SDongjin Kim#include <dt-bindings/gpio/gpio.h>
9fd358326SDongjin Kim#include <dt-bindings/leds/common.h>
10fd358326SDongjin Kim#include <dt-bindings/pinctrl/rockchip.h>
11913404aaSAurelien Jarno#include <dt-bindings/soc/rockchip,vop2.h>
12fd358326SDongjin Kim#include "rk3568.dtsi"
13fd358326SDongjin Kim
14fd358326SDongjin Kim/ {
15fd358326SDongjin Kim	model = "Hardkernel ODROID-M1";
16fd358326SDongjin Kim	compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568";
17fd358326SDongjin Kim
18fd358326SDongjin Kim	aliases {
19fd358326SDongjin Kim		ethernet0 = &gmac0;
20fd358326SDongjin Kim		i2c0 = &i2c3;
21fd358326SDongjin Kim		i2c3 = &i2c0;
22fd358326SDongjin Kim		mmc0 = &sdhci;
23fd358326SDongjin Kim		mmc1 = &sdmmc0;
24fd358326SDongjin Kim		serial0 = &uart1;
25fd358326SDongjin Kim		serial1 = &uart0;
26fd358326SDongjin Kim	};
27fd358326SDongjin Kim
28fd358326SDongjin Kim	chosen {
29fd358326SDongjin Kim		stdout-path = "serial2:1500000n8";
30fd358326SDongjin Kim	};
31fd358326SDongjin Kim
32fd358326SDongjin Kim	dc_12v: dc-12v-regulator {
33fd358326SDongjin Kim		compatible = "regulator-fixed";
34fd358326SDongjin Kim		regulator-name = "dc_12v";
35fd358326SDongjin Kim		regulator-always-on;
36fd358326SDongjin Kim		regulator-boot-on;
37fd358326SDongjin Kim		regulator-min-microvolt = <12000000>;
38fd358326SDongjin Kim		regulator-max-microvolt = <12000000>;
39fd358326SDongjin Kim	};
40fd358326SDongjin Kim
41913404aaSAurelien Jarno	hdmi-con {
42913404aaSAurelien Jarno		compatible = "hdmi-connector";
43913404aaSAurelien Jarno		type = "a";
44913404aaSAurelien Jarno
45913404aaSAurelien Jarno		port {
46913404aaSAurelien Jarno			hdmi_con_in: endpoint {
47913404aaSAurelien Jarno				remote-endpoint = <&hdmi_out_con>;
48913404aaSAurelien Jarno			};
49913404aaSAurelien Jarno		};
50913404aaSAurelien Jarno	};
51913404aaSAurelien Jarno
52*d6882992SAurelien Jarno	ir-receiver {
53*d6882992SAurelien Jarno		compatible = "gpio-ir-receiver";
54*d6882992SAurelien Jarno		gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
55*d6882992SAurelien Jarno		pinctrl-names = "default";
56*d6882992SAurelien Jarno		pinctrl-0 = <&ir_receiver_pin>;
57*d6882992SAurelien Jarno	};
58*d6882992SAurelien Jarno
59fd358326SDongjin Kim	leds {
60fd358326SDongjin Kim		compatible = "gpio-leds";
61fd358326SDongjin Kim
62fd358326SDongjin Kim		led_power: led-0 {
63fd358326SDongjin Kim			gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
64fd358326SDongjin Kim			function = LED_FUNCTION_POWER;
65fd358326SDongjin Kim			color = <LED_COLOR_ID_RED>;
66fd358326SDongjin Kim			default-state = "keep";
67fd358326SDongjin Kim			linux,default-trigger = "default-on";
68fd358326SDongjin Kim			pinctrl-names = "default";
69fd358326SDongjin Kim			pinctrl-0 = <&led_power_pin>;
70fd358326SDongjin Kim		};
71fd358326SDongjin Kim		led_work: led-1 {
72fd358326SDongjin Kim			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
73fd358326SDongjin Kim			function = LED_FUNCTION_HEARTBEAT;
74fd358326SDongjin Kim			color = <LED_COLOR_ID_BLUE>;
75fd358326SDongjin Kim			linux,default-trigger = "heartbeat";
76fd358326SDongjin Kim			pinctrl-names = "default";
77fd358326SDongjin Kim			pinctrl-0 = <&led_work_pin>;
78fd358326SDongjin Kim		};
79fd358326SDongjin Kim	};
80fd358326SDongjin Kim
8178f85844SAurelien Jarno	rk809-sound {
8278f85844SAurelien Jarno		compatible = "simple-audio-card";
8378f85844SAurelien Jarno		pinctrl-names = "default";
8478f85844SAurelien Jarno		pinctrl-0 = <&hp_det_pin>;
8578f85844SAurelien Jarno		simple-audio-card,name = "Analog RK817";
8678f85844SAurelien Jarno		simple-audio-card,format = "i2s";
8778f85844SAurelien Jarno		simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
8878f85844SAurelien Jarno		simple-audio-card,mclk-fs = <256>;
8978f85844SAurelien Jarno		simple-audio-card,widgets =
9078f85844SAurelien Jarno			"Headphone", "Headphones",
9178f85844SAurelien Jarno			"Speaker", "Speaker";
9278f85844SAurelien Jarno		simple-audio-card,routing =
9378f85844SAurelien Jarno			"Headphones", "HPOL",
9478f85844SAurelien Jarno			"Headphones", "HPOR",
9578f85844SAurelien Jarno			"Speaker", "SPKO";
9678f85844SAurelien Jarno
9778f85844SAurelien Jarno		simple-audio-card,cpu {
9878f85844SAurelien Jarno			sound-dai = <&i2s1_8ch>;
9978f85844SAurelien Jarno		};
10078f85844SAurelien Jarno
10178f85844SAurelien Jarno		simple-audio-card,codec {
10278f85844SAurelien Jarno			sound-dai = <&rk809>;
10378f85844SAurelien Jarno		};
10478f85844SAurelien Jarno	};
10578f85844SAurelien Jarno
10635b28582SAurelien Jarno	vcc3v3_pcie: vcc3v3-pcie-regulator {
10735b28582SAurelien Jarno		compatible = "regulator-fixed";
10835b28582SAurelien Jarno		regulator-name = "vcc3v3_pcie";
10935b28582SAurelien Jarno		enable-active-high;
11035b28582SAurelien Jarno		gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
11135b28582SAurelien Jarno		pinctrl-names = "default";
11235b28582SAurelien Jarno		pinctrl-0 = <&vcc3v3_pcie_en_pin>;
11335b28582SAurelien Jarno		regulator-min-microvolt = <3300000>;
11435b28582SAurelien Jarno		regulator-max-microvolt = <3300000>;
11535b28582SAurelien Jarno		startup-delay-us = <5000>;
11635b28582SAurelien Jarno		vin-supply = <&vcc3v3_sys>;
11735b28582SAurelien Jarno	};
11835b28582SAurelien Jarno
119fd358326SDongjin Kim	vcc3v3_sys: vcc3v3-sys-regulator {
120fd358326SDongjin Kim		compatible = "regulator-fixed";
121fd358326SDongjin Kim		regulator-name = "vcc3v3_sys";
122fd358326SDongjin Kim		regulator-always-on;
123fd358326SDongjin Kim		regulator-boot-on;
124fd358326SDongjin Kim		regulator-min-microvolt = <3300000>;
125fd358326SDongjin Kim		regulator-max-microvolt = <3300000>;
126fd358326SDongjin Kim		vin-supply = <&dc_12v>;
127fd358326SDongjin Kim	};
1284685d7b6SAurelien Jarno
1294685d7b6SAurelien Jarno	vcc5v0_sys: vcc5v0-sys-regulator {
1304685d7b6SAurelien Jarno		compatible = "regulator-fixed";
1314685d7b6SAurelien Jarno		regulator-name = "vcc5v0_sys";
1324685d7b6SAurelien Jarno		regulator-always-on;
1334685d7b6SAurelien Jarno		regulator-boot-on;
1344685d7b6SAurelien Jarno		regulator-min-microvolt = <5000000>;
1354685d7b6SAurelien Jarno		regulator-max-microvolt = <5000000>;
1364685d7b6SAurelien Jarno		vin-supply = <&dc_12v>;
1374685d7b6SAurelien Jarno	};
1384685d7b6SAurelien Jarno
1394685d7b6SAurelien Jarno	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
1404685d7b6SAurelien Jarno		compatible = "regulator-fixed";
1414685d7b6SAurelien Jarno		regulator-name = "vcc5v0_usb_host";
1424685d7b6SAurelien Jarno		enable-active-high;
1434685d7b6SAurelien Jarno		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
1444685d7b6SAurelien Jarno		pinctrl-names = "default";
1454685d7b6SAurelien Jarno		pinctrl-0 = <&vcc5v0_usb_host_en_pin>;
1464685d7b6SAurelien Jarno		regulator-min-microvolt = <5000000>;
1474685d7b6SAurelien Jarno		regulator-max-microvolt = <5000000>;
1484685d7b6SAurelien Jarno		vin-supply = <&vcc5v0_sys>;
1494685d7b6SAurelien Jarno	};
1509984ef56SAurelien Jarno
1519984ef56SAurelien Jarno	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
1529984ef56SAurelien Jarno		compatible = "regulator-fixed";
1539984ef56SAurelien Jarno		regulator-name = "vcc5v0_usb_otg";
1549984ef56SAurelien Jarno		enable-active-high;
1559984ef56SAurelien Jarno		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
1569984ef56SAurelien Jarno		pinctrl-names = "default";
1579984ef56SAurelien Jarno		pinctrl-0 = <&vcc5v0_usb_otg_en_pin>;
1589984ef56SAurelien Jarno		regulator-min-microvolt = <5000000>;
1599984ef56SAurelien Jarno		regulator-max-microvolt = <5000000>;
1609984ef56SAurelien Jarno		vin-supply = <&vcc5v0_sys>;
1619984ef56SAurelien Jarno	};
1629984ef56SAurelien Jarno};
1639984ef56SAurelien Jarno
1649984ef56SAurelien Jarno&combphy0 {
1659984ef56SAurelien Jarno	/* Used for USB3 */
1669984ef56SAurelien Jarno	phy-supply = <&vcc5v0_usb_host>;
1679984ef56SAurelien Jarno	status = "okay";
1689984ef56SAurelien Jarno};
1699984ef56SAurelien Jarno
1709984ef56SAurelien Jarno&combphy1 {
1719984ef56SAurelien Jarno	/* Used for USB3 */
1729984ef56SAurelien Jarno	phy-supply = <&vcc5v0_usb_otg>;
1739984ef56SAurelien Jarno	status = "okay";
174fd358326SDongjin Kim};
175fd358326SDongjin Kim
1766a5a04d5SAurelien Jarno&combphy2 {
1776a5a04d5SAurelien Jarno	/* used for SATA */
1786a5a04d5SAurelien Jarno	status = "okay";
1796a5a04d5SAurelien Jarno};
1806a5a04d5SAurelien Jarno
181fd358326SDongjin Kim&cpu0 {
182fd358326SDongjin Kim	cpu-supply = <&vdd_cpu>;
183fd358326SDongjin Kim};
184fd358326SDongjin Kim
185fd358326SDongjin Kim&cpu1 {
186fd358326SDongjin Kim	cpu-supply = <&vdd_cpu>;
187fd358326SDongjin Kim};
188fd358326SDongjin Kim
189fd358326SDongjin Kim&cpu2 {
190fd358326SDongjin Kim	cpu-supply = <&vdd_cpu>;
191fd358326SDongjin Kim};
192fd358326SDongjin Kim
193fd358326SDongjin Kim&cpu3 {
194fd358326SDongjin Kim	cpu-supply = <&vdd_cpu>;
195fd358326SDongjin Kim};
196fd358326SDongjin Kim
197fd358326SDongjin Kim&gmac0 {
198fd358326SDongjin Kim	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
199fd358326SDongjin Kim	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
200fd358326SDongjin Kim	assigned-clock-rates = <0>, <125000000>;
201fd358326SDongjin Kim	clock_in_out = "output";
202fd358326SDongjin Kim	phy-handle = <&rgmii_phy0>;
203fd358326SDongjin Kim	phy-mode = "rgmii";
204fd358326SDongjin Kim	phy-supply = <&vcc3v3_sys>;
205fd358326SDongjin Kim	pinctrl-names = "default";
206fd358326SDongjin Kim	pinctrl-0 = <&gmac0_miim
207fd358326SDongjin Kim		     &gmac0_tx_bus2
208fd358326SDongjin Kim		     &gmac0_rx_bus2
209fd358326SDongjin Kim		     &gmac0_rgmii_clk
210fd358326SDongjin Kim		     &gmac0_rgmii_bus>;
211fd358326SDongjin Kim	status = "okay";
212fd358326SDongjin Kim
213fd358326SDongjin Kim	tx_delay = <0x4f>;
214fd358326SDongjin Kim	rx_delay = <0x2d>;
215fd358326SDongjin Kim};
216fd358326SDongjin Kim
217cb80b345SAurelien Jarno&gpu {
218cb80b345SAurelien Jarno	mali-supply = <&vdd_gpu>;
219cb80b345SAurelien Jarno	status = "okay";
220cb80b345SAurelien Jarno};
221cb80b345SAurelien Jarno
222913404aaSAurelien Jarno&hdmi {
223913404aaSAurelien Jarno	avdd-0v9-supply = <&vdda0v9_image>;
224913404aaSAurelien Jarno	avdd-1v8-supply = <&vcca1v8_image>;
225913404aaSAurelien Jarno	status = "okay";
226913404aaSAurelien Jarno};
227913404aaSAurelien Jarno
228913404aaSAurelien Jarno&hdmi_in {
229913404aaSAurelien Jarno	hdmi_in_vp0: endpoint {
230913404aaSAurelien Jarno		remote-endpoint = <&vp0_out_hdmi>;
231913404aaSAurelien Jarno	};
232913404aaSAurelien Jarno};
233913404aaSAurelien Jarno
234913404aaSAurelien Jarno&hdmi_out {
235913404aaSAurelien Jarno	hdmi_out_con: endpoint {
236913404aaSAurelien Jarno		remote-endpoint = <&hdmi_con_in>;
237913404aaSAurelien Jarno	};
238913404aaSAurelien Jarno};
239913404aaSAurelien Jarno
2401ca7ddddSAurelien Jarno&hdmi_sound {
2411ca7ddddSAurelien Jarno	status = "okay";
2421ca7ddddSAurelien Jarno};
2431ca7ddddSAurelien Jarno
244fd358326SDongjin Kim&i2c0 {
245fd358326SDongjin Kim	status = "okay";
246fd358326SDongjin Kim
247fd358326SDongjin Kim	vdd_cpu: regulator@1c {
248fd358326SDongjin Kim		compatible = "tcs,tcs4525";
249fd358326SDongjin Kim		reg = <0x1c>;
250fd358326SDongjin Kim		fcs,suspend-voltage-selector = <1>;
251fd358326SDongjin Kim		regulator-name = "vdd_cpu";
252fd358326SDongjin Kim		regulator-always-on;
253fd358326SDongjin Kim		regulator-boot-on;
254fd358326SDongjin Kim		regulator-min-microvolt = <800000>;
255fd358326SDongjin Kim		regulator-max-microvolt = <1150000>;
256fd358326SDongjin Kim		regulator-ramp-delay = <2300>;
257fd358326SDongjin Kim		vin-supply = <&vcc3v3_sys>;
258fd358326SDongjin Kim
259fd358326SDongjin Kim		regulator-state-mem {
260fd358326SDongjin Kim			regulator-off-in-suspend;
261fd358326SDongjin Kim		};
262fd358326SDongjin Kim	};
263fd358326SDongjin Kim
264fd358326SDongjin Kim	rk809: pmic@20 {
265fd358326SDongjin Kim		compatible = "rockchip,rk809";
266fd358326SDongjin Kim		reg = <0x20>;
267fd358326SDongjin Kim		interrupt-parent = <&gpio0>;
268fd358326SDongjin Kim		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
26978f85844SAurelien Jarno		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
27078f85844SAurelien Jarno		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
271fd358326SDongjin Kim		#clock-cells = <1>;
27278f85844SAurelien Jarno		clock-names = "mclk";
27378f85844SAurelien Jarno		clocks = <&cru I2S1_MCLKOUT_TX>;
274fd358326SDongjin Kim		pinctrl-names = "default";
27578f85844SAurelien Jarno		pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
276fd358326SDongjin Kim		rockchip,system-power-controller;
27778f85844SAurelien Jarno		#sound-dai-cells = <0>;
278fd358326SDongjin Kim		vcc1-supply = <&vcc3v3_sys>;
279fd358326SDongjin Kim		vcc2-supply = <&vcc3v3_sys>;
280fd358326SDongjin Kim		vcc3-supply = <&vcc3v3_sys>;
281fd358326SDongjin Kim		vcc4-supply = <&vcc3v3_sys>;
282fd358326SDongjin Kim		vcc5-supply = <&vcc3v3_sys>;
283fd358326SDongjin Kim		vcc6-supply = <&vcc3v3_sys>;
284fd358326SDongjin Kim		vcc7-supply = <&vcc3v3_sys>;
285fd358326SDongjin Kim		vcc8-supply = <&vcc3v3_sys>;
286fd358326SDongjin Kim		vcc9-supply = <&vcc3v3_sys>;
287fd358326SDongjin Kim		wakeup-source;
288fd358326SDongjin Kim
289fd358326SDongjin Kim		regulators {
290fd358326SDongjin Kim			vdd_logic: DCDC_REG1 {
291fd358326SDongjin Kim				regulator-name = "vdd_logic";
292fd358326SDongjin Kim				regulator-always-on;
293fd358326SDongjin Kim				regulator-boot-on;
294fd358326SDongjin Kim				regulator-initial-mode = <0x2>;
295fd358326SDongjin Kim				regulator-min-microvolt = <500000>;
296fd358326SDongjin Kim				regulator-max-microvolt = <1350000>;
297fd358326SDongjin Kim				regulator-ramp-delay = <6001>;
298fd358326SDongjin Kim
299fd358326SDongjin Kim				regulator-state-mem {
300fd358326SDongjin Kim					regulator-off-in-suspend;
301fd358326SDongjin Kim				};
302fd358326SDongjin Kim			};
303fd358326SDongjin Kim
304fd358326SDongjin Kim			vdd_gpu: DCDC_REG2 {
305fd358326SDongjin Kim				regulator-name = "vdd_gpu";
306fd358326SDongjin Kim				regulator-always-on;
307fd358326SDongjin Kim				regulator-initial-mode = <0x2>;
308fd358326SDongjin Kim				regulator-min-microvolt = <500000>;
309fd358326SDongjin Kim				regulator-max-microvolt = <1350000>;
310fd358326SDongjin Kim				regulator-ramp-delay = <6001>;
311fd358326SDongjin Kim
312fd358326SDongjin Kim				regulator-state-mem {
313fd358326SDongjin Kim					regulator-off-in-suspend;
314fd358326SDongjin Kim				};
315fd358326SDongjin Kim			};
316fd358326SDongjin Kim
317fd358326SDongjin Kim			vcc_ddr: DCDC_REG3 {
318fd358326SDongjin Kim				regulator-name = "vcc_ddr";
319fd358326SDongjin Kim				regulator-always-on;
320fd358326SDongjin Kim				regulator-boot-on;
321fd358326SDongjin Kim				regulator-initial-mode = <0x2>;
322fd358326SDongjin Kim
323fd358326SDongjin Kim				regulator-state-mem {
324fd358326SDongjin Kim					regulator-on-in-suspend;
325fd358326SDongjin Kim				};
326fd358326SDongjin Kim			};
327fd358326SDongjin Kim
328fd358326SDongjin Kim			vdd_npu: DCDC_REG4 {
329fd358326SDongjin Kim				regulator-name = "vdd_npu";
330fd358326SDongjin Kim				regulator-initial-mode = <0x2>;
331fd358326SDongjin Kim				regulator-min-microvolt = <500000>;
332fd358326SDongjin Kim				regulator-max-microvolt = <1350000>;
333fd358326SDongjin Kim				regulator-ramp-delay = <6001>;
334fd358326SDongjin Kim
335fd358326SDongjin Kim				regulator-state-mem {
336fd358326SDongjin Kim					regulator-off-in-suspend;
337fd358326SDongjin Kim				};
338fd358326SDongjin Kim			};
339fd358326SDongjin Kim
340fd358326SDongjin Kim			vcc_1v8: DCDC_REG5 {
341fd358326SDongjin Kim				regulator-name = "vcc_1v8";
342fd358326SDongjin Kim				regulator-always-on;
343fd358326SDongjin Kim				regulator-boot-on;
344fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
345fd358326SDongjin Kim				regulator-max-microvolt = <1800000>;
346fd358326SDongjin Kim
347fd358326SDongjin Kim				regulator-state-mem {
348fd358326SDongjin Kim					regulator-off-in-suspend;
349fd358326SDongjin Kim				};
350fd358326SDongjin Kim			};
351fd358326SDongjin Kim
352fd358326SDongjin Kim			vdda0v9_image: LDO_REG1 {
353fd358326SDongjin Kim				regulator-name = "vdda0v9_image";
354fd358326SDongjin Kim				regulator-always-on;
355fd358326SDongjin Kim				regulator-min-microvolt = <900000>;
356fd358326SDongjin Kim				regulator-max-microvolt = <900000>;
357fd358326SDongjin Kim
358fd358326SDongjin Kim				regulator-state-mem {
359fd358326SDongjin Kim					regulator-off-in-suspend;
360fd358326SDongjin Kim				};
361fd358326SDongjin Kim			};
362fd358326SDongjin Kim
363fd358326SDongjin Kim			vdda_0v9: LDO_REG2 {
364fd358326SDongjin Kim				regulator-name = "vdda_0v9";
365fd358326SDongjin Kim				regulator-always-on;
366fd358326SDongjin Kim				regulator-boot-on;
367fd358326SDongjin Kim				regulator-min-microvolt = <900000>;
368fd358326SDongjin Kim				regulator-max-microvolt = <900000>;
369fd358326SDongjin Kim
370fd358326SDongjin Kim				regulator-state-mem {
371fd358326SDongjin Kim					regulator-off-in-suspend;
372fd358326SDongjin Kim				};
373fd358326SDongjin Kim			};
374fd358326SDongjin Kim
375fd358326SDongjin Kim			vdda0v9_pmu: LDO_REG3 {
376fd358326SDongjin Kim				regulator-name = "vdda0v9_pmu";
377fd358326SDongjin Kim				regulator-always-on;
378fd358326SDongjin Kim				regulator-boot-on;
379fd358326SDongjin Kim				regulator-min-microvolt = <900000>;
380fd358326SDongjin Kim				regulator-max-microvolt = <900000>;
381fd358326SDongjin Kim
382fd358326SDongjin Kim				regulator-state-mem {
383fd358326SDongjin Kim					regulator-on-in-suspend;
384fd358326SDongjin Kim					regulator-suspend-microvolt = <900000>;
385fd358326SDongjin Kim				};
386fd358326SDongjin Kim			};
387fd358326SDongjin Kim
388fd358326SDongjin Kim			vccio_acodec: LDO_REG4 {
389fd358326SDongjin Kim				regulator-name = "vccio_acodec";
390fd358326SDongjin Kim				regulator-always-on;
391fd358326SDongjin Kim				regulator-boot-on;
392fd358326SDongjin Kim				regulator-min-microvolt = <3300000>;
393fd358326SDongjin Kim				regulator-max-microvolt = <3300000>;
394fd358326SDongjin Kim
395fd358326SDongjin Kim				regulator-state-mem {
396fd358326SDongjin Kim					regulator-off-in-suspend;
397fd358326SDongjin Kim				};
398fd358326SDongjin Kim			};
399fd358326SDongjin Kim
400fd358326SDongjin Kim			vccio_sd: LDO_REG5 {
401fd358326SDongjin Kim				regulator-name = "vccio_sd";
402fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
403fd358326SDongjin Kim				regulator-max-microvolt = <3300000>;
404fd358326SDongjin Kim
405fd358326SDongjin Kim				regulator-state-mem {
406fd358326SDongjin Kim					regulator-off-in-suspend;
407fd358326SDongjin Kim				};
408fd358326SDongjin Kim			};
409fd358326SDongjin Kim
410fd358326SDongjin Kim			vcc3v3_pmu: LDO_REG6 {
411fd358326SDongjin Kim				regulator-name = "vcc3v3_pmu";
412fd358326SDongjin Kim				regulator-always-on;
413fd358326SDongjin Kim				regulator-boot-on;
414fd358326SDongjin Kim				regulator-min-microvolt = <3300000>;
415fd358326SDongjin Kim				regulator-max-microvolt = <3300000>;
416fd358326SDongjin Kim
417fd358326SDongjin Kim				regulator-state-mem {
418fd358326SDongjin Kim					regulator-on-in-suspend;
419fd358326SDongjin Kim					regulator-suspend-microvolt = <3300000>;
420fd358326SDongjin Kim				};
421fd358326SDongjin Kim			};
422fd358326SDongjin Kim
423fd358326SDongjin Kim			vcca_1v8: LDO_REG7 {
424fd358326SDongjin Kim				regulator-name = "vcca_1v8";
425fd358326SDongjin Kim				regulator-always-on;
426fd358326SDongjin Kim				regulator-boot-on;
427fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
428fd358326SDongjin Kim				regulator-max-microvolt = <1800000>;
429fd358326SDongjin Kim
430fd358326SDongjin Kim				regulator-state-mem {
431fd358326SDongjin Kim					regulator-off-in-suspend;
432fd358326SDongjin Kim				};
433fd358326SDongjin Kim			};
434fd358326SDongjin Kim
435fd358326SDongjin Kim			vcca1v8_pmu: LDO_REG8 {
436fd358326SDongjin Kim				regulator-name = "vcca1v8_pmu";
437fd358326SDongjin Kim				regulator-always-on;
438fd358326SDongjin Kim				regulator-boot-on;
439fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
440fd358326SDongjin Kim				regulator-max-microvolt = <1800000>;
441fd358326SDongjin Kim
442fd358326SDongjin Kim				regulator-state-mem {
443fd358326SDongjin Kim					regulator-on-in-suspend;
444fd358326SDongjin Kim					regulator-suspend-microvolt = <1800000>;
445fd358326SDongjin Kim				};
446fd358326SDongjin Kim			};
447fd358326SDongjin Kim
448fd358326SDongjin Kim			vcca1v8_image: LDO_REG9 {
449fd358326SDongjin Kim				regulator-name = "vcca1v8_image";
450fd358326SDongjin Kim				regulator-always-on;
451fd358326SDongjin Kim				regulator-min-microvolt = <1800000>;
452fd358326SDongjin Kim				regulator-max-microvolt = <1800000>;
453fd358326SDongjin Kim
454fd358326SDongjin Kim				regulator-state-mem {
455fd358326SDongjin Kim					regulator-off-in-suspend;
456fd358326SDongjin Kim				};
457fd358326SDongjin Kim			};
458fd358326SDongjin Kim
459fd358326SDongjin Kim			vcc_3v3: SWITCH_REG1 {
460fd358326SDongjin Kim				regulator-name = "vcc_3v3";
461fd358326SDongjin Kim				regulator-always-on;
462fd358326SDongjin Kim				regulator-boot-on;
463fd358326SDongjin Kim
464fd358326SDongjin Kim				regulator-state-mem {
465fd358326SDongjin Kim					regulator-off-in-suspend;
466fd358326SDongjin Kim				};
467fd358326SDongjin Kim			};
468fd358326SDongjin Kim
469fd358326SDongjin Kim			vcc3v3_sd: SWITCH_REG2 {
470fd358326SDongjin Kim				regulator-name = "vcc3v3_sd";
471fd358326SDongjin Kim
472fd358326SDongjin Kim				regulator-state-mem {
473fd358326SDongjin Kim					regulator-off-in-suspend;
474fd358326SDongjin Kim				};
475fd358326SDongjin Kim			};
476fd358326SDongjin Kim		};
477fd358326SDongjin Kim	};
478fd358326SDongjin Kim};
479fd358326SDongjin Kim
4801ca7ddddSAurelien Jarno&i2s0_8ch {
4811ca7ddddSAurelien Jarno	status = "okay";
4821ca7ddddSAurelien Jarno};
4831ca7ddddSAurelien Jarno
48478f85844SAurelien Jarno&i2s1_8ch {
48578f85844SAurelien Jarno	rockchip,trcm-sync-tx-only;
48678f85844SAurelien Jarno	status = "okay";
48778f85844SAurelien Jarno};
48878f85844SAurelien Jarno
489fd358326SDongjin Kim&mdio0 {
490fd358326SDongjin Kim	rgmii_phy0: ethernet-phy@0 {
491fd358326SDongjin Kim		compatible = "ethernet-phy-ieee802.3-c22";
492fd358326SDongjin Kim		reg = <0x0>;
493fd358326SDongjin Kim		reset-assert-us = <20000>;
494fd358326SDongjin Kim		reset-deassert-us = <100000>;
495fd358326SDongjin Kim		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
496fd358326SDongjin Kim	};
497fd358326SDongjin Kim};
498fd358326SDongjin Kim
49935b28582SAurelien Jarno&pcie30phy {
50035b28582SAurelien Jarno	status = "okay";
50135b28582SAurelien Jarno};
50235b28582SAurelien Jarno
50335b28582SAurelien Jarno&pcie3x2 {
50435b28582SAurelien Jarno	pinctrl-names = "default";
50535b28582SAurelien Jarno	pinctrl-0 = <&pcie_reset_pin>;
50635b28582SAurelien Jarno	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
50735b28582SAurelien Jarno	vpcie3v3-supply = <&vcc3v3_pcie>;
50835b28582SAurelien Jarno	status = "okay";
50935b28582SAurelien Jarno};
51035b28582SAurelien Jarno
511fd358326SDongjin Kim&pinctrl {
5129f96204bSAurelien Jarno	fspi {
5139f96204bSAurelien Jarno		fspi_dual_io_pins: fspi-dual-io-pins {
5149f96204bSAurelien Jarno			rockchip,pins =
5159f96204bSAurelien Jarno				/* fspi_clk */
5169f96204bSAurelien Jarno				<1 RK_PD0 1 &pcfg_pull_none>,
5179f96204bSAurelien Jarno				/* fspi_cs0n */
5189f96204bSAurelien Jarno				<1 RK_PD3 1 &pcfg_pull_none>,
5199f96204bSAurelien Jarno				/* fspi_d0 */
5209f96204bSAurelien Jarno				<1 RK_PD1 1 &pcfg_pull_none>,
5219f96204bSAurelien Jarno				/* fspi_d1 */
5229f96204bSAurelien Jarno				<1 RK_PD2 1 &pcfg_pull_none>;
5239f96204bSAurelien Jarno		};
5249f96204bSAurelien Jarno	};
5259f96204bSAurelien Jarno
526*d6882992SAurelien Jarno	ir-receiver {
527*d6882992SAurelien Jarno		ir_receiver_pin: ir-receiver-pin {
528*d6882992SAurelien Jarno			/* external pullup to VCC3V3_SYS */
529*d6882992SAurelien Jarno			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
530*d6882992SAurelien Jarno		};
531*d6882992SAurelien Jarno	};
532*d6882992SAurelien Jarno
533fd358326SDongjin Kim	leds {
534fd358326SDongjin Kim		led_power_pin: led-power-pin {
535fd358326SDongjin Kim			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
536fd358326SDongjin Kim		};
537fd358326SDongjin Kim		led_work_pin: led-work-pin {
538fd358326SDongjin Kim			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
539fd358326SDongjin Kim		};
540fd358326SDongjin Kim	};
541fd358326SDongjin Kim
54235b28582SAurelien Jarno	pcie {
54335b28582SAurelien Jarno		pcie_reset_pin: pcie-reset-pin {
54435b28582SAurelien Jarno			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
54535b28582SAurelien Jarno		};
54635b28582SAurelien Jarno		vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
54735b28582SAurelien Jarno			rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
54835b28582SAurelien Jarno		};
54935b28582SAurelien Jarno	};
55035b28582SAurelien Jarno
551fd358326SDongjin Kim	pmic {
552fd358326SDongjin Kim		pmic_int_l: pmic-int-l {
553fd358326SDongjin Kim			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
554fd358326SDongjin Kim		};
555fd358326SDongjin Kim	};
55678f85844SAurelien Jarno
55778f85844SAurelien Jarno	rk809 {
55878f85844SAurelien Jarno		hp_det_pin: hp-det-pin {
55978f85844SAurelien Jarno			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
56078f85844SAurelien Jarno		};
56178f85844SAurelien Jarno	};
5624685d7b6SAurelien Jarno
5634685d7b6SAurelien Jarno	usb {
5644685d7b6SAurelien Jarno		vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin {
5654685d7b6SAurelien Jarno			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
5664685d7b6SAurelien Jarno		};
5679984ef56SAurelien Jarno		vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin {
5684685d7b6SAurelien Jarno			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
5694685d7b6SAurelien Jarno		};
5704685d7b6SAurelien Jarno	};
571fd358326SDongjin Kim};
572fd358326SDongjin Kim
573fd358326SDongjin Kim&pmu_io_domains {
574fd358326SDongjin Kim	pmuio1-supply = <&vcc3v3_pmu>;
575fd358326SDongjin Kim	pmuio2-supply = <&vcc3v3_pmu>;
576fd358326SDongjin Kim	vccio1-supply = <&vccio_acodec>;
577fd358326SDongjin Kim	vccio2-supply = <&vcc_1v8>;
578fd358326SDongjin Kim	vccio3-supply = <&vccio_sd>;
579fd358326SDongjin Kim	vccio4-supply = <&vcc_1v8>;
580fd358326SDongjin Kim	vccio5-supply = <&vcc_3v3>;
581fd358326SDongjin Kim	vccio6-supply = <&vcc_3v3>;
582fd358326SDongjin Kim	vccio7-supply = <&vcc_3v3>;
583fd358326SDongjin Kim	status = "okay";
584fd358326SDongjin Kim};
585fd358326SDongjin Kim
586fd358326SDongjin Kim&saradc {
587fd358326SDongjin Kim	vref-supply = <&vcca_1v8>;
588fd358326SDongjin Kim	status = "okay";
589fd358326SDongjin Kim};
590fd358326SDongjin Kim
5916a5a04d5SAurelien Jarno&sata2 {
5926a5a04d5SAurelien Jarno	status = "okay";
5936a5a04d5SAurelien Jarno};
5946a5a04d5SAurelien Jarno
595fd358326SDongjin Kim&sdhci {
596fd358326SDongjin Kim	bus-width = <8>;
597fd358326SDongjin Kim	max-frequency = <200000000>;
598fd358326SDongjin Kim	non-removable;
599fd358326SDongjin Kim	pinctrl-names = "default";
600fd358326SDongjin Kim	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>;
601fd358326SDongjin Kim	vmmc-supply = <&vcc_3v3>;
602fd358326SDongjin Kim	vqmmc-supply = <&vcc_1v8>;
603fd358326SDongjin Kim	status = "okay";
604fd358326SDongjin Kim};
605fd358326SDongjin Kim
606fd358326SDongjin Kim&sdmmc0 {
607fd358326SDongjin Kim	bus-width = <4>;
608fd358326SDongjin Kim	cap-sd-highspeed;
609fd358326SDongjin Kim	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
610fd358326SDongjin Kim	disable-wp;
611fd358326SDongjin Kim	pinctrl-names = "default";
612fd358326SDongjin Kim	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
613fd358326SDongjin Kim	sd-uhs-sdr50;
614fd358326SDongjin Kim	vmmc-supply = <&vcc3v3_sd>;
615fd358326SDongjin Kim	vqmmc-supply = <&vccio_sd>;
616fd358326SDongjin Kim	status = "okay";
617fd358326SDongjin Kim};
618fd358326SDongjin Kim
6199f96204bSAurelien Jarno&sfc {
6209f96204bSAurelien Jarno	/* Dual I/O mode as the D2 pin conflicts with the eMMC */
6219f96204bSAurelien Jarno	pinctrl-0 = <&fspi_dual_io_pins>;
6229f96204bSAurelien Jarno	pinctrl-names = "default";
6239f96204bSAurelien Jarno	#address-cells = <1>;
6249f96204bSAurelien Jarno	#size-cells = <0>;
6259f96204bSAurelien Jarno	status = "okay";
6269f96204bSAurelien Jarno
6279f96204bSAurelien Jarno	flash@0 {
6289f96204bSAurelien Jarno		compatible = "jedec,spi-nor";
6299f96204bSAurelien Jarno		reg = <0>;
6309f96204bSAurelien Jarno		spi-max-frequency = <100000000>;
6319f96204bSAurelien Jarno		spi-rx-bus-width = <2>;
6329f96204bSAurelien Jarno		spi-tx-bus-width = <1>;
6339f96204bSAurelien Jarno
6349f96204bSAurelien Jarno		partitions {
6359f96204bSAurelien Jarno			compatible = "fixed-partitions";
6369f96204bSAurelien Jarno			#address-cells = <1>;
6379f96204bSAurelien Jarno			#size-cells = <1>;
6389f96204bSAurelien Jarno
6399f96204bSAurelien Jarno			partition@0 {
6409f96204bSAurelien Jarno				label = "SPL";
6419f96204bSAurelien Jarno				reg = <0x0 0xe0000>;
6429f96204bSAurelien Jarno			};
6439f96204bSAurelien Jarno			partition@e0000 {
6449f96204bSAurelien Jarno				label = "U-Boot Env";
6459f96204bSAurelien Jarno				reg = <0xe0000 0x20000>;
6469f96204bSAurelien Jarno			};
6479f96204bSAurelien Jarno			partition@100000 {
6489f96204bSAurelien Jarno				label = "U-Boot";
6499f96204bSAurelien Jarno				reg = <0x100000 0x200000>;
6509f96204bSAurelien Jarno			};
6519f96204bSAurelien Jarno			partition@300000 {
6529f96204bSAurelien Jarno				label = "splash";
6539f96204bSAurelien Jarno				reg = <0x300000 0x100000>;
6549f96204bSAurelien Jarno			};
6559f96204bSAurelien Jarno			partition@400000 {
6569f96204bSAurelien Jarno				label = "Filesystem";
6579f96204bSAurelien Jarno				reg = <0x400000 0xc00000>;
6589f96204bSAurelien Jarno			};
6599f96204bSAurelien Jarno		};
6609f96204bSAurelien Jarno	};
6619f96204bSAurelien Jarno};
6629f96204bSAurelien Jarno
663f5511bd8SAurelien Jarno&tsadc {
664f5511bd8SAurelien Jarno	rockchip,hw-tshut-mode = <1>;
665f5511bd8SAurelien Jarno	rockchip,hw-tshut-polarity = <0>;
666f5511bd8SAurelien Jarno	status = "okay";
667f5511bd8SAurelien Jarno};
668f5511bd8SAurelien Jarno
669fd358326SDongjin Kim&uart2 {
670fd358326SDongjin Kim	status = "okay";
671fd358326SDongjin Kim};
672913404aaSAurelien Jarno
6734685d7b6SAurelien Jarno&usb_host0_ehci {
6744685d7b6SAurelien Jarno	status = "okay";
6754685d7b6SAurelien Jarno};
6764685d7b6SAurelien Jarno
6774685d7b6SAurelien Jarno&usb_host0_ohci {
6784685d7b6SAurelien Jarno	status = "okay";
6794685d7b6SAurelien Jarno};
6804685d7b6SAurelien Jarno
6819984ef56SAurelien Jarno&usb_host0_xhci {
6829984ef56SAurelien Jarno	dr_mode = "host";
6839984ef56SAurelien Jarno	status = "okay";
6849984ef56SAurelien Jarno};
6859984ef56SAurelien Jarno
6864685d7b6SAurelien Jarno&usb_host1_ehci {
6874685d7b6SAurelien Jarno	status = "okay";
6884685d7b6SAurelien Jarno};
6894685d7b6SAurelien Jarno
6904685d7b6SAurelien Jarno&usb_host1_ohci {
6914685d7b6SAurelien Jarno	status = "okay";
6924685d7b6SAurelien Jarno};
6934685d7b6SAurelien Jarno
6949984ef56SAurelien Jarno&usb_host1_xhci {
6959984ef56SAurelien Jarno	status = "okay";
6969984ef56SAurelien Jarno};
6979984ef56SAurelien Jarno
6989984ef56SAurelien Jarno&usb2phy0 {
6999984ef56SAurelien Jarno	status = "okay";
7009984ef56SAurelien Jarno};
7019984ef56SAurelien Jarno
7029984ef56SAurelien Jarno&usb2phy0_host {
7039984ef56SAurelien Jarno	phy-supply = <&vcc5v0_usb_host>;
7049984ef56SAurelien Jarno	status = "okay";
7059984ef56SAurelien Jarno};
7069984ef56SAurelien Jarno
7079984ef56SAurelien Jarno&usb2phy0_otg {
7089984ef56SAurelien Jarno	phy-supply = <&vcc5v0_usb_otg>;
7099984ef56SAurelien Jarno	status = "okay";
7109984ef56SAurelien Jarno};
7119984ef56SAurelien Jarno
7124685d7b6SAurelien Jarno&usb2phy1 {
7134685d7b6SAurelien Jarno	status = "okay";
7144685d7b6SAurelien Jarno};
7154685d7b6SAurelien Jarno
7164685d7b6SAurelien Jarno&usb2phy1_host {
7174685d7b6SAurelien Jarno	phy-supply = <&vcc5v0_usb_host>;
7184685d7b6SAurelien Jarno	status = "okay";
7194685d7b6SAurelien Jarno};
7204685d7b6SAurelien Jarno
7214685d7b6SAurelien Jarno&usb2phy1_otg {
7224685d7b6SAurelien Jarno	phy-supply = <&vcc5v0_usb_host>;
7234685d7b6SAurelien Jarno	status = "okay";
7244685d7b6SAurelien Jarno};
7254685d7b6SAurelien Jarno
726913404aaSAurelien Jarno&vop {
727913404aaSAurelien Jarno	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
728913404aaSAurelien Jarno	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
729913404aaSAurelien Jarno	status = "okay";
730913404aaSAurelien Jarno};
731913404aaSAurelien Jarno
732913404aaSAurelien Jarno&vop_mmu {
733913404aaSAurelien Jarno	status = "okay";
734913404aaSAurelien Jarno};
735913404aaSAurelien Jarno
736913404aaSAurelien Jarno&vp0 {
737913404aaSAurelien Jarno	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
738913404aaSAurelien Jarno		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
739913404aaSAurelien Jarno		remote-endpoint = <&hdmi_in_vp0>;
740913404aaSAurelien Jarno	};
741913404aaSAurelien Jarno};
742