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/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dtegra20-dc.txt28 * delay between panel_vdd-rise and data-rise
29 * delay between data-rise and backlight_vdd-rise
30 * delay between backlight_vdd and pwm-rise
31 * delay between pwm-rise and backlight_en-rise
/openbmc/linux/drivers/gpu/drm/panel/
H A Dpanel-feiyang-fy07024di26a30d.c58 /* T1 (dvdd start + dvdd rise) 0 < T1 <= 10ms */ in feiyang_prepare()
65 /* T3 (dvdd rise + avdd start + avdd rise) T3 >= 20ms */ in feiyang_prepare()
71 * T5 + T6 (avdd rise + video & logic signal rise) in feiyang_prepare()
78 /* T12 (video & logic signal rise + backlight rise) T12 >= 200ms */ in feiyang_prepare()
98 /* T12 (video & logic signal rise + backlight rise) T12 >= 200ms */ in feiyang_enable()
133 /* T11 (dvdd rise to fall) 0 < T11 <= 10ms */ in feiyang_unprepare()
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dcirrus,cs42l42.yaml75 cirrus,ts-dbnc-rise:
162 If present this sets the rate that the HS bias should rise and fall.
163 The actual rise and fall times depend on external hardware (the
164 datasheet gives several rise and fall time examples).
166 0 - Fast rise time; slow, load-dependent fall time
219 cirrus,ts-dbnc-rise = <CS42L42_TS_DBNCE_1000>;
H A Dcirrus,cs42l43.yaml138 cirrus,tip-rise-db-ms:
168 cirrus,ring-rise-db-ms:
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Doffload.h42 * @system_time: system time on air rise
43 * @tsf: TSF on air rise
44 * @beacon_timestamp: beacon on air rise
H A Drx.h32 * @system_timestamp: GP2 at on air rise
33 * @timestamp: TSF at on air rise
34 * @beacon_time_stamp: beacon at on-air rise
509 * @gp2_on_air_rise: GP2 timer value on air rise (INA)
516 * TSF value on air rise (INA), only valid if
606 * @gp2_on_air_rise: GP2 timer value on air rise (INA)
613 * TSF value on air rise (INA), only valid if
789 * @on_air_rise_time: GP2 during on air rise
814 * @on_air_rise_time: GP2 during on air rise
/openbmc/linux/drivers/gpio/
H A Dgpio-mt7621.c112 u32 rise, fall, high, low; in mediatek_gpio_irq_unmask() local
117 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); in mediatek_gpio_irq_unmask()
121 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising)); in mediatek_gpio_irq_unmask()
135 u32 rise, fall, high, low; in mediatek_gpio_irq_mask() local
138 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); in mediatek_gpio_irq_mask()
143 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin)); in mediatek_gpio_irq_mask()
H A Dgpio-mlxbf2.c293 bool rise = false; in mlxbf2_gpio_irq_set_type() local
299 rise = true; in mlxbf2_gpio_irq_set_type()
302 rise = true; in mlxbf2_gpio_irq_set_type()
318 if (rise) { in mlxbf2_gpio_irq_set_type()
/openbmc/qemu/hw/intc/
H A Domap_intc.c111 uint32_t rise; in omap_set_intr() local
117 rise = ~bank->irqs & (1 << n); in omap_set_intr()
119 rise &= ~bank->inputs; in omap_set_intr()
122 if (rise) { in omap_set_intr()
123 bank->irqs |= rise; in omap_set_intr()
128 rise = bank->sens_edge & bank->irqs & (1 << n); in omap_set_intr()
129 bank->irqs &= ~rise; in omap_set_intr()
/openbmc/u-boot/include/
H A Dddr_spd.h129 unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient
132 unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient
135 unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient
137 unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient
139 unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient
142 unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient
145 unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient
148 unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient
150 unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient
158 unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient
[all …]
/openbmc/linux/Documentation/leds/
H A Dleds-sc27xx.rst12 hardware pattern, which is used to configure the rise time,
17 format, we should set brightness as 0 for rise stage, fall
H A Dleds-cht-wcove.rst27 The rise and fall times must be the same value.
/openbmc/qemu/include/hw/intc/
H A Dimx_avic.h33 #define NIAD (1<<20) /* Normal Interrupt Arbiter Rise ARM level */
34 #define FIAD (1<<19) /* Fast Interrupt Arbiter Rise ARM level */
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-mux-ltc4306.txt24 - ltc,downstream-accelerators-enable: Enables the rise time accelerators
26 - ltc,upstream-accelerators-enable: Enables the rise time accelerators
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8mq-usb-phy.yaml44 fsl,phy-tx-rise-tune-percent:
46 Adjusts the rise/fall time duration of the HS waveform relative to
H A Dqcom,usb-snps-femto-v2.yaml113 qcom,hs-rise-fall-time-bp:
115 This adjusts the rise/fall times of the high-speed waveform.
H A Dphy-stm32-usbphyc.yaml115 description: Enables the FS rise/fall tuning option
119 description: Enables the HS rise/fall reduction feature
/openbmc/u-boot/drivers/usb/dwc3/
H A Ddwc3-omap.c276 dev_dbg(omap->dev, "DRVVBUS Rise\n"); in dwc3_omap_interrupt()
279 dev_dbg(omap->dev, "CHRGVBUS Rise\n"); in dwc3_omap_interrupt()
282 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n"); in dwc3_omap_interrupt()
285 dev_dbg(omap->dev, "IDPULLUP Rise\n"); in dwc3_omap_interrupt()
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra114.c20 #define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */
21 #define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
1202 /* Use hardwired rise->rise & fall->fall clock propagation delays */ in tegra114_clock_tune_cpu_trimmers_high()
1226 * Use software-specified rise->rise & fall->fall clock in tegra114_clock_tune_cpu_trimmers_low()
1251 /* Increment the rise->rise clock delay by four steps */ in tegra114_clock_tune_cpu_trimmers_init()
1258 * Use the rise->rise clock propagation delay specified in the in tegra114_clock_tune_cpu_trimmers_init()
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dci-hdrc-usb2.yaml301 fsl,picophy-rise-fall-time-adjust:
303 HS Transmitter Rise/Fall Time Adjustment. Adjust the rise/fall times
304 of the high-speed transmitter waveform. It has no unit. The rise/fall
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt92 address and data to DEV_WEn rise.
100 data after DEV_WEn rise.
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/cpuid/
H A Dcpuid_20230614.bb5 UMC, NexGen, Rise, and SiS CPUs"
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dstarfive,jh7100-wdt.yaml17 output(WDOGINT) will rise when counter is 0. The counter will reload
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-gru-kevin.dts166 /* These are relatively safe rise/fall times. */
182 /* These are relatively safe rise/fall times. */
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-kevin.dts185 /* These are relatively safe rise/fall times. */
201 /* These are relatively safe rise/fall times. */

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