1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale i.MX8MQ USB3 PHY 8 9maintainers: 10 - Li Jun <jun.li@nxp.com> 11 12properties: 13 compatible: 14 enum: 15 - fsl,imx8mq-usb-phy 16 - fsl,imx8mp-usb-phy 17 18 reg: 19 maxItems: 1 20 21 "#phy-cells": 22 const: 0 23 24 clocks: 25 maxItems: 1 26 27 clock-names: 28 items: 29 - const: phy 30 31 power-domains: 32 maxItems: 1 33 34 vbus-supply: 35 description: 36 A phandle to the regulator for USB VBUS. 37 38 fsl,phy-tx-vref-tune-percent: 39 description: 40 Tunes the HS DC level relative to the nominal level 41 minimum: 94 42 maximum: 124 43 44 fsl,phy-tx-rise-tune-percent: 45 description: 46 Adjusts the rise/fall time duration of the HS waveform relative to 47 its nominal value 48 minimum: 97 49 maximum: 103 50 51 fsl,phy-tx-preemp-amp-tune-microamp: 52 description: 53 Adjust amount of current sourced to DPn and DMn after a J-to-K 54 or K-to-J transition. Default is 0 (disabled). 55 minimum: 0 56 maximum: 1800 57 58 fsl,phy-tx-vboost-level-microvolt: 59 description: 60 Adjust the boosted transmit launch pk-pk differential amplitude 61 minimum: 880 62 maximum: 1120 63 64 fsl,phy-comp-dis-tune-percent: 65 description: 66 Adjust the voltage level used to detect a disconnect event at the host 67 relative to the nominal value 68 minimum: 91 69 maximum: 115 70 71 fsl,phy-pcs-tx-deemph-3p5db-attenuation-db: 72 description: 73 Adjust TX de-emphasis attenuation in dB at nominal 74 3.5dB point as per USB specification 75 $ref: /schemas/types.yaml#/definitions/uint32 76 minimum: 0 77 maximum: 36 78 79 fsl,phy-pcs-tx-swing-full-percent: 80 description: 81 Scaling of the voltage defined by fsl,phy-tx-vboost-level-microvolt 82 minimum: 0 83 maximum: 100 84 85required: 86 - compatible 87 - reg 88 - "#phy-cells" 89 - clocks 90 - clock-names 91 92additionalProperties: false 93 94examples: 95 - | 96 #include <dt-bindings/clock/imx8mq-clock.h> 97 usb3_phy0: phy@381f0040 { 98 compatible = "fsl,imx8mq-usb-phy"; 99 reg = <0x381f0040 0x40>; 100 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; 101 clock-names = "phy"; 102 #phy-cells = <0>; 103 }; 104