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/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml1 # SPDX-License-Identifier: BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V SBI PMU events
10 - Atish Patra <atishp@rivosinc.com>
13 The SBI PMU extension allows supervisor software to configure, start and
15 capabilities of performance analysis tools, such as perf, if the SBI PMU
20 Without the event to counter mappings, the SBI PMU extension cannot be used.
29 For information on the SBI specification see the section "Performance
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/openbmc/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/openbmc/u-boot/board/emulation/qemu-riscv/
H A Dqemu-riscv.c1 // SPDX-License-Identifier: GPL-2.0+
36 ret = ofnode_read_u64(chosen_node, "riscv,kernel-start", in board_late_init()
39 ret = ofnode_read_u32(chosen_node, "riscv,kernel-start", in board_late_init()
53 * QEMU specifies the location of Linux (supplied with the -kernel argument)
54 * in the device tree using the riscv,kernel-start and riscv,kernel-end
55 * properties. We currently rely on the SBI implementation of BBL to run
61 * This workaround can be removed, once we do not require BBL for its SBI
73 ret = fdt_setprop_u64(blob, chosen_offset, "riscv,kernel-start", 0); in ft_board_setup()
75 ret = fdt_setprop_u32(blob, chosen_offset, "riscv,kernel-start", 0); in ft_board_setup()
81 ret = fdt_setprop_u64(blob, chosen_offset, "riscv,kernel-end", 0); in ft_board_setup()
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
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/openbmc/linux/drivers/clocksource/
H A Dtimer-riscv.c1 // SPDX-License-Identifier: GPL-2.0
6 * All RISC-V systems have a timer attached to every hart. These timers can
7 * either be read from the "time" and "timeh" CSRs, and can use the SBI to
11 #define pr_fmt(fmt) "riscv-timer: " fmt
22 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <clocksource/timer-riscv.h>
28 #include <asm/sbi.h>
93 ce->cpumask = cpumask_of(cpu); in riscv_timer_starting_cpu()
94 ce->irq = riscv_clock_event_irq; in riscv_timer_starting_cpu()
96 ce->features |= CLOCK_EVT_FEAT_C3STOP; in riscv_timer_starting_cpu()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
180 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
203 32-bit free running decrementing counters.
238 bool "Integrator-AP timer driver" if COMPILE_TEST
241 Enables support for the Integrator-AP timer.
266 available on many OMAP-like platforms.
285 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
289 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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/openbmc/linux/drivers/cpuidle/
H A Dcpuidle-riscv-sbi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V SBI CPU idle driver.
9 #define pr_fmt(fmt) "cpuidle-riscv-sbi: " fmt
25 #include <asm/sbi.h>
52 data->available = true; in sbi_set_domain_state()
53 data->state = state; in sbi_set_domain_state()
60 return data->state; in sbi_get_domain_state()
67 data->available = false; in sbi_clear_domain_state()
74 return data->available; in sbi_is_domain_state_available()
115 u32 *states = data->states; in __sbi_enter_domain_idle_state()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-y += cpuidle.o driver.o governor.o sysfs.o governors/
7 obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
8 obj-$(CONFIG_DT_IDLE_STATES) += dt_idle_states.o
9 obj-$(CONFIG_DT_IDLE_GENPD) += dt_idle_genpd.o
10 obj-$(CONFIG_ARCH_HAS_CPU_RELAX) += poll_state.o
11 obj-$(CONFIG_HALTPOLL_CPUIDLE) += cpuidle-haltpoll.o
15 obj-$(CONFIG_ARM_MVEBU_V7_CPUIDLE) += cpuidle-mvebu-v7.o
16 obj-$(CONFIG_ARM_BIG_LITTLE_CPUIDLE) += cpuidle-big_little.o
17 obj-$(CONFIG_ARM_CLPS711X_CPUIDLE) += cpuidle-clps711x.o
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Driscv,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
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/openbmc/linux/arch/riscv/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
13 config RISCV config
169 # https://github.com/llvm/llvm-project/commit/6ab8927931851bb42b2c93a00801dc499d7d9b1e
176 depends on $(cc-option,-fpatchable-function-entry=8)
186 # VA_BITS - PAGE_SHIFT - 3
199 # set if we are running in S-mode and can use SBI calls
206 bool "MMU-based Paged Memory Management Support"
209 Select if you want MMU-based virtualised addressing space
286 This enables function pointer support for non-standard noncoherent
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/openbmc/linux/arch/riscv/kernel/
H A Dsbi-ipi.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #define pr_fmt(fmt) "riscv: " fmt
14 #include <asm/sbi.h>
69 * via generic IPI-Mux in sbi_ipi_init()
72 "irqchip/sbi-ipi:starting", in sbi_ipi_init()
76 pr_info("providing IPIs using SBI IPI extension\n"); in sbi_ipi_init()
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <asm/sbi.h>
26 * Returns the hart ID of the given device tree node, or -ENODEV if the node
27 * isn't an enabled and valid RISC-V hart node.
36 return -ENODEV; in riscv_of_processor_hartid()
44 return -ENODEV; in riscv_of_processor_hartid()
53 if (!of_device_is_compatible(node, "riscv")) { in riscv_early_of_processor_hartid()
55 return -ENODEV; in riscv_early_of_processor_hartid()
61 return -ENODEV; in riscv_early_of_processor_hartid()
66 return -ENODEV; in riscv_early_of_processor_hartid()
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H A Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/sbi.h>
27 #include "copy-unaligned.h"
29 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
33 #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
40 /* Per-cpu ISA extensions. */
47 * riscv_isa_extension_base() - Get base extension word
63 * __riscv_isa_extension_available() - Check whether given extension
88 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_isa_extension_check()
91 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_isa_extension_check()
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H A Dsys_riscv.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <asm/sbi.h>
17 #include <asm-generic/mman-common.h>
26 return -EINVAL; in riscv_sys_mmap()
29 offset >> (PAGE_SHIFT - page_shift_offset)); in riscv_sys_mmap()
55 * Allows the instruction cache to be flushed from userspace. Despite RISC-V
60 * thread->hart mappings), so we've defined a RISC-V specific system call to
73 return -EINVAL; in SYSCALL_DEFINE3()
75 flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL); in SYSCALL_DEFINE3()
82 * are supported by the hardware. See Documentation/riscv/hwprobe.rst for more
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/openbmc/linux/arch/riscv/mm/
H A Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <asm/sbi.h>
30 * Performs an icache flush for the given MM context. RISC-V has no direct
34 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
47 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
60 if (mm == current->active_mm && local) { in flush_icache_mm()
64 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm()
87 if (!test_bit(PG_dcache_clean, &folio->flags)) { in flush_icache_pte()
89 set_bit(PG_dcache_clean, &folio->flags); in flush_icache_pte()
129 /* set block-size for cbom and/or cboz extension if available */ in riscv_init_cbo_blocksizes()
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/openbmc/openbmc/poky/meta/conf/machine/include/riscv/
H A Dqemuriscv.inc1 PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot"
4 require conf/machine/include/riscv/tune-riscv.inc
18 MACHINE_EXTRA_RRECOMMENDS += " kernel-modules"
22 RISCV_SBI_PAYLOAD ?= "${KERNEL_IMAGETYPE}-${MACHINE}.bin"
28 QB_SMP ?= "-smp 4"
29 QB_KERNEL_CMDLINE_APPEND = "earlycon=sbi"
30 QB_MACHINE = "-machine virt"
32 QB_TAP_OPT = "-netdev tap,id=net0,ifname=@TAP@,script=no,downscript=no"
33 QB_NETWORK_DEVICE = "-device virtio-net-device,netdev=net0,mac=@MAC@"
34 QB_ROOTFS_OPT = "-drive id=disk0,file=@ROOTFS@,if=none,format=raw -device virtio-blk-device,drive=d…
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/openbmc/openbmc/poky/meta/recipes-bsp/opensbi/
H A Dopensbi_1.5.1.bb1 SUMMARY = "RISC-V Open Source Supervisor Binary Interface (OpenSBI)"
2 …-source and extensible implementation of the RISC-V SBI specification for a platform specific firm…
3 HOMEPAGE = "https://github.com/riscv/opensbi"
4 LICENSE = "BSD-2-Clause"
7 require opensbi-payloads.inc
9 inherit autotools-brokensep deploy
12 SRC_URI = "git://github.com/riscv/opensbi.git;branch=release-1.5.x;protocol=https"
30 rm -r ${D}/include
31 rm -r ${D}/lib*
32 rm -r ${D}/share/opensbi/*/${RISCV_SBI_PLAT}/firmware/payloads
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/openbmc/linux/drivers/perf/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
56 Say y if you want to use CPU performance monitors on ARM-based
60 depends on RISCV
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H A Driscv_pmu_sbi.c1 // SPDX-License-Identifier: GPL-2.0
3 * RISC-V performance counter support.
11 #define pr_fmt(fmt) "riscv-pmu-sbi: " fmt
24 #include <asm/sbi.h>
35 PMU_FORMAT_ATTR(event, "config:0-47");
58 * RISC-V doesn't have heterogeneous harts yet. This need to be part of
281 return (info->type == SBI_PMU_CTR_TYPE_FW) ? true : false; in pmu_sbi_ctr_is_fw()
296 return -EINVAL; in riscv_pmu_get_hpm_info()
302 if (!hpm_width && info->csr != CSR_CYCLE && info->csr != CSR_INSTRET) in riscv_pmu_get_hpm_info()
303 hpm_width = info->width; in riscv_pmu_get_hpm_info()
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/openbmc/linux/include/linux/perf/
H A Driscv_pmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define RISCV_OP_UNSUPP (-EOPNOTSUPP)
24 #define RISCV_PMU_SBI_PDEV_NAME "riscv-pmu-sbi"
25 #define RISCV_PMU_LEGACY_PDEV_NAME "riscv-pmu-legacy"
/openbmc/qemu/pc-bios/
H A DREADME1 - SeaBIOS (bios.bin) is the successor of pc bios.
4 - The VGA BIOS and the Cirrus VGA BIOS come from the LGPL VGA bios
7 - OpenBIOS (http://www.openbios.org/) is a free (GPL v2) portable
9 1275-1994 (referred to as Open Firmware) compliant firmware.
14 - SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware
17 built from git tag qemu-slof-20230918.
19 - VOF (Virtual Open Firmware) is a minimalistic firmware to work with
20 -machine pseries,x-vof=on. When enabled, the firmware acts as a slim shim and
23 - The PXE roms come from the iPXE project. Built with BANNER_TIME 0.
24 Sources available at http://ipxe.org. Vendor:Device ID -> ROM mapping:
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/openbmc/linux/drivers/irqchip/
H A Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
29 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
36 * On RISC-V systems local interrupts are masked or unmasked by writing
44 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
49 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
55 * Andes specific S-mode local interrupt causes (hwirq) in andes_intc_irq_mask()
56 * are defined as (256 + n) and controlled by n-th bit in andes_intc_irq_mask()
59 unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); in andes_intc_irq_mask()
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/openbmc/linux/Documentation/riscv/
H A Dboot.rst1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
32 The RISC-V kernel expects:
37 -------------------------------------
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/openbmc/linux/drivers/tty/serial/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_SERIAL_CORE) += serial_base.o
7 serial_base-y := serial_core.o serial_base_bus.o serial_ctrl.o serial_port.o
9 obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o
10 obj-$(CONFIG_SERIAL_EARLYCON_SEMIHOST) += earlycon-semihost.o
11 obj-$(CONFIG_SERIAL_EARLYCON_RISCV_SBI) += earlycon-riscv-sbi.o
16 obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
17 obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o
18 obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o
19 obj-$(CONFIG_SERIAL_SUNSU) += sunsu.o
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/openbmc/qemu/hw/riscv/
H A Dboot.c2 * QEMU RISC-V Boot Helper
23 #include "qemu/error-report.h"
24 #include "exec/cpu-defs.h"
27 #include "hw/riscv/boot.h"
28 #include "hw/riscv/boot_opensbi.h"
39 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]); in riscv_is_32bit()
40 return mcc->misa_mxl_max == MXL_RV32; in riscv_is_32bit()
44 * Return the per-socket PLIC hart topology configuration string
54 CPURISCVState *env = &RISCV_CPU(cs)->env; in riscv_plic_hart_config_string()
101 error_report("Unable to find the RISC-V BIOS \"%s\"", in riscv_find_bios()
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