riscv/mm/cacheflush.c

1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <asm/sbi.h>
30  * Performs an icache flush for the given MM context.  RISC-V has no direct
34  * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
47 	mask = &mm->context.icache_stale_mask;  in flush_icache_mm()
60 	if (mm == current->active_mm && local) {  in flush_icache_mm()
64 		 * and scheduling this MM context on that hart.  Sending an SBI  in flush_icache_mm()
87 	if (!test_bit(PG_dcache_clean, &folio->flags)) {  in flush_icache_pte()
89 		set_bit(PG_dcache_clean, &folio->flags);  in flush_icache_pte()
129 		/* set block-size for cbom and/or cboz extension if available */  in riscv_init_cbo_blocksizes()
130 		cbo_get_block_size(node, "riscv,cbom-block-size",  in riscv_init_cbo_blocksizes()
132 		cbo_get_block_size(node, "riscv,cboz-block-size",  in riscv_init_cbo_blocksizes()