drivers/clocksource/timer-riscv.c

1 // SPDX-License-Identifier: GPL-2.0
6  * All RISC-V systems have a timer attached to every hart.  These timers can
7  * either be read from the "time" and "timeh" CSRs, and can use the SBI to
11 #define pr_fmt(fmt) "riscv-timer: " fmt
22 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <clocksource/timer-riscv.h>
28 #include <asm/sbi.h>
93 	ce->cpumask = cpumask_of(cpu);  in riscv_timer_starting_cpu()
94 	ce->irq = riscv_clock_event_irq;  in riscv_timer_starting_cpu()
96 		ce->features |= CLOCK_EVT_FEAT_C3STOP;  in riscv_timer_starting_cpu()
117 /* called directly from the low-level interrupt handler */
123 	evdev->event_handler(evdev);  in riscv_timer_interrupt()
138 		return -ENODEV;  in riscv_timer_init_common()
144 		return -ENODEV;  in riscv_timer_init_common()
149 		pr_err("RISCV timer registration failed [%d]\n", error);  in riscv_timer_init_common()
157 				    "riscv-timer", &riscv_clock_event);  in riscv_timer_init_common()
164 		pr_info("Timer interrupt in S-mode is available via sstc extension\n");  in riscv_timer_init_common()
169 			 "clockevents/riscv/timer:starting",  in riscv_timer_init_common()
172 		pr_err("cpu hp setup state failed for RISCV timer [%d]\n",  in riscv_timer_init_common()
200 	child = of_find_compatible_node(NULL, NULL, "riscv,timer");  in riscv_timer_init_dt()
203 					"riscv,timer-cannot-wake-cpu");  in riscv_timer_init_dt()
210 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);