1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/sbi.h>
27 #include "copy-unaligned.h"
29 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
33 #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
40 /* Per-cpu ISA extensions. */
47  * riscv_isa_extension_base() - Get base extension word
63  * __riscv_isa_extension_available() - Check whether given extension
88 			pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n");  in riscv_isa_extension_check()
91 			pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");  in riscv_isa_extension_check()
97 			pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n");  in riscv_isa_extension_check()
100 			pr_err("cboz-block-size present, but is not a power-of-2\n");  in riscv_isa_extension_check()
119  * Ordinarily, for in-kernel data structures, this order is unimportant but
125  * 1. All multi-letter extensions must be separated from other extensions by an
129  *    single-letter extensions and before any higher-privileged extensions.
136  * 3. Standard supervisor-level extensions (starting with 'S') must be listed
137  *    after standard unprivileged extensions.  If multiple supervisor-level
140  * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
141  *    after any lower-privileged, standard extensions.  If multiple
142  *    machine-level extensions are listed, they must be ordered
145  * 5. Non-standard extensions (starting with 'X') must be listed after all
146  *    standard extensions. If multiple non-standard extensions are listed, they
208 			 * Workaround for invalid single-letter 's' & 'u'(QEMU).  in riscv_parse_isa_string()
210 			 * not valid ISA extensions. It works until multi-letter  in riscv_parse_isa_string()
213 			if (ext[-1] != '_' && ext[1] == 'u') {  in riscv_parse_isa_string()
226 			 * As multi-letter extensions must be split from other multi-letter  in riscv_parse_isa_string()
227 			 * extensions with an "_", the end of a multi-letter extension will  in riscv_parse_isa_string()
229 			 * multi-letter extension.  in riscv_parse_isa_string()
240 			 * A simple re-increment solves this problem.  in riscv_parse_isa_string()
251 			if (!isdigit(ext_end[-1]))  in riscv_parse_isa_string()
254 			while (isdigit(*--ext_end))  in riscv_parse_isa_string()
257 			if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) {  in riscv_parse_isa_string()
262 			while (isdigit(*--ext_end))  in riscv_parse_isa_string()
269 			 * Things are a little easier for single-letter extensions, as they  in riscv_parse_isa_string()
276 			 * If we are already on a non-digit, there is nothing to do. Either  in riscv_parse_isa_string()
277 			 * we have a multi-letter extension's _, or the start of an  in riscv_parse_isa_string()
301 				--isa;  in riscv_parse_isa_string()
314 		 * on meeting a non-alphanumeric character, an extra increment is needed  in riscv_parse_isa_string()
315 		 * where the succeeding extension is a multi-letter prefixed with an "_".  in riscv_parse_isa_string()
322 			if ((ext_end - ext == strlen(name)) &&			\  in riscv_parse_isa_string()
325 				set_bit(bit, isainfo->isa);			\  in riscv_parse_isa_string()
331 			int nr = tolower(*ext) - 'a';  in riscv_parse_isa_string()
335 				set_bit(nr, isainfo->isa);  in riscv_parse_isa_string()
377 			rc = of_property_read_string(node, "riscv,isa", &isa);  in riscv_fill_hwcap_from_isa_string()
380 				pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");  in riscv_fill_hwcap_from_isa_string()
386 				pr_warn("Unable to get ISA for the hart - %d\n", cpu);  in riscv_fill_hwcap_from_isa_string()
395 		 * port & dt-bindings were upstreamed, and so can be set  in riscv_fill_hwcap_from_isa_string()
396 		 * unconditionally where `i` is in riscv,isa on DT systems.  in riscv_fill_hwcap_from_isa_string()
399 			set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);  in riscv_fill_hwcap_from_isa_string()
400 			set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);  in riscv_fill_hwcap_from_isa_string()
401 			set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);  in riscv_fill_hwcap_from_isa_string()
402 			set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);  in riscv_fill_hwcap_from_isa_string()
407 		 * just the standard V-1.0 but vendors aren't well behaved.  in riscv_fill_hwcap_from_isa_string()
408 		 * Many vendors with T-Head CPU cores which implement the 0.7.1  in riscv_fill_hwcap_from_isa_string()
410 		 * CPU cores with the ratified spec will contain non-zero  in riscv_fill_hwcap_from_isa_string()
415 			clear_bit(RISCV_ISA_EXT_v, isainfo->isa);  in riscv_fill_hwcap_from_isa_string()
429 			bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);  in riscv_fill_hwcap_from_isa_string()
431 			bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);  in riscv_fill_hwcap_from_isa_string()
453 		if (!of_property_present(cpu_node, "riscv,isa-extensions")) {  in riscv_fill_hwcap_from_ext_list()
459 			if (of_property_match_string(cpu_node, "riscv,isa-extensions",  in riscv_fill_hwcap_from_ext_list()
470 			set_bit(riscv_isa_ext[i].id, isainfo->isa);  in riscv_fill_hwcap_from_ext_list()
485 			bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);  in riscv_fill_hwcap_from_ext_list()
487 			bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);  in riscv_fill_hwcap_from_ext_list()
491 		return -ENOENT;  in riscv_fill_hwcap_from_ext_list()
514 	isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;  in riscv_fill_hwcap()
515 	isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;  in riscv_fill_hwcap()
516 	isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;  in riscv_fill_hwcap()
517 	isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;  in riscv_fill_hwcap()
518 	isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;  in riscv_fill_hwcap()
519 	isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;  in riscv_fill_hwcap()
520 	isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;  in riscv_fill_hwcap()
528 			pr_info("Falling back to deprecated \"riscv,isa\"\n");  in riscv_fill_hwcap()
557 	pr_info("riscv: base ISA extensions %s\n", print_str);  in riscv_fill_hwcap()
563 	pr_info("riscv: ELF capabilities %s\n", print_str);  in riscv_fill_hwcap()
570 	hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1));  in riscv_get_elf_hwcap()
605 	word_cycles = -1ULL;  in check_unaligned_access()
625 		if ((end_cycles - start_cycles) < word_cycles)  in check_unaligned_access()
626 			word_cycles = end_cycles - start_cycles;  in check_unaligned_access()
629 	byte_cycles = -1ULL;  in check_unaligned_access()
641 		if ((end_cycles - start_cycles) < byte_cycles)  in check_unaligned_access()
642 			byte_cycles = end_cycles - start_cycles;  in check_unaligned_access()
683  * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
684  * patch site is for an erratum, identified by the 32-bit patch ID. When
686  * further break down patch ID into two 16-bit numbers. The lower 16 bits
690  * patching on a per-site basis will provide non-zero values and implement
725 		if (alt->vendor_id != 0)  in riscv_cpufeature_patch_func()
728 		id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);  in riscv_cpufeature_patch_func()
738 		value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);  in riscv_cpufeature_patch_func()
746 		patch_text_nosync(oldptr, altptr, alt->alt_len);  in riscv_cpufeature_patch_func()
747 		riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);  in riscv_cpufeature_patch_func()