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/openbmc/linux/include/sound/
H A Dcs8427.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #define CS8427_REG_AUTOINC 0x80 /* flag - autoincrement */
34 #define CS8427_REG_QSUBCODE 0x14 /* 0x14-0x1d (10 bytes) */
63 #define CS8427_AESBP (1<<5) /* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */
65 #define CS8427_TXDSERIAL (1<<3) /* TXD - serial audio input port */
66 #define CS8427_TXAES3DRECEIVER (2<<3) /* TXD - AES3 receiver */
68 #define CS8427_SPDSERIAL (1<<1) /* SPD - serial audio input port */
69 #define CS8427_SPDAES3RECEIVER (2<<1) /* SPD - AES3 receiver */
88 #define CS8427_SIRESMASK (3<<4) /* Resolution of the input data for right justified formats */
89 #define CS8427_SIRES24 (0<<4) /* SIRES 24-bit */
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H A Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
31 #define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
32 #define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
33 #define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
34 #define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
35 #define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
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H A Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
38 #define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */
39 #define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */
40 #define AK4114_REG_QSUB_ABSMIN 0x1d /* Q-subcode absolute minute */
41 #define AK4114_REG_QSUB_ABSSEC 0x1e /* Q-subcode absolute second */
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H A Dak4113.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
50 /* Q-subcode address + control */
52 /* Q-subcode track */
54 /* Q-subcode index */
56 /* Q-subcode minute */
58 /* Q-subcode second */
60 /* Q-subcode frame */
62 /* Q-subcode zero */
64 /* Q-subcode absolute minute */
66 /* Q-subcode absolute second */
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H A Dsoc-dai.h1 /* SPDX-License-Identifier: GPL-2.0
3 * linux/sound/soc-dai.h -- ALSA SoC Layer
5 * Copyright: 2005-2008 Wolfson Microelectronics. PLC.
35 /* left and right justified also known as MSB and LSB respectively */
66 * define GATED -> CONT. GATED will be selected if both are selected.
82 * - "normal" polarity means signal is available at rising edge of BCLK
83 * - "inverted" polarity means signal is available at falling edge of BCLK
86 * - I2S: frame consists of left then right channel data. Left channel starts
87 * with falling FSYNC edge, right channel starts with rising FSYNC edge.
88 * - Left/Right Justified: frame consists of left then right channel data.
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/openbmc/u-boot/include/
H A Di2s.h1 /* SPDX-License-Identifier: GPL-2.0+ */
17 #define SND_SOC_DAIFMT_RIGHT_J 2 /* Right Justified mode */
18 #define SND_SOC_DAIFMT_LEFT_J 3 /* Left Justified mode */
24 /* left and right justified also known as MSB and LSB respectively */
93 * tx_data() - Transmit audio data
98 * @return 0 if OK, -ve on error
103 #define i2s_get_ops(dev) ((struct i2s_ops *)(dev)->driver->ops)
106 * i2s_tx_data() - Transmit audio data
111 * @return 0 if OK, -ve on error
121 * @return int value 0 for success, -1 in case of error
/openbmc/linux/Documentation/sound/soc/
H A Ddai.rst28 left/right clock (LRC) synchronise the link. I2S is flexible in that either the
35 I2S has several different operating modes:-
41 Left Justified
44 Right Justified
58 Common PCM operating modes:-
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra20-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 Justified Mode, Right Justified Mode, and DSP mode formats.
15 - Thierry Reding <treding@nvidia.com>
16 - Jon Hunter <jonathanh@nvidia.com>
20 const: nvidia,tegra20-i2s
28 reset-names:
40 dma-names:
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H A Dst,stm32-sai.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/st,stm32-sai.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Olivier Moysan <olivier.moysan@foss.st.com>
14 protocols as I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC'97.
15 The SAI contains two independent audio sub-blocks. Each sub-block has
21 - st,stm32f4-sai
22 - st,stm32h7-sai
26 - description: Base address and size of SAI common register set.
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H A Dfsl,ssi.txt4 be programmed in AC97, I2S, left-justified, or right-justified modes.
7 - compatible: Compatible list, should contain one of the following
9 fsl,mpc8610-ssi
10 fsl,imx51-ssi
11 fsl,imx35-ssi
12 fsl,imx21-ssi
13 - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
14 - reg: Offset and length of the register set for the device.
15 - interrupts: <a b> where a is the interrupt number and b is a
21 - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
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H A Dcirrus,ep9301-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/cirrus,ep9301-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 I2S CODECs’, ADCs/DACs, and the ARM Core. The controller supports I2S, Left-
12 and Right-Justified DSP formats.
15 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
18 - $ref: dai-common.yaml#
22 const: cirrus,ep9301-i2s
24 '#sound-dai-cells':
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H A Dti,tlv320aic3x.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 TLV320AIC3x are a series of low-power stereo audio codecs with stereo
13 single-ended or fully differential configurations.
16 data bus is programmable for I2S, left/right-justified, DSP, or TDM modes.
44 - Jai Luthra <j-luthra@ti.com>
49 - ti,tlv320aic3x
50 - ti,tlv320aic33
51 - ti,tlv320aic3007
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/openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/css/
H A Dbootstrap.min.css3 * Copyright 2011-2015 Twitter, Inc.
5 …-family:sans-serif;-webkit-text-size-adjust:100%;-ms-text-size-adjust:100%}body{margin:0}article,a…
H A Dbootstrap.css3 * Copyright 2011-2015 Twitter, Inc.
8 font-family: sans-serif;
9 -webkit-text-size-adjust: 100%;
10 -ms-text-size-adjust: 100%;
34 display: inline-block;
35 vertical-align: baseline;
46 background-color: transparent;
53 border-bottom: 1px dotted;
57 font-weight: bold;
60 font-style: italic;
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H A Dbootstrap.css.map1 …-prefixes.less","less/mixins/tab-focus.less","less/mixins/image.less","less/type.less","less/mixin…
/openbmc/linux/sound/soc/codecs/
H A Dtlv320aic26.h1 /* SPDX-License-Identifier: GPL-2.0 */
79 AIC26_DATFM_RIGHTJ = 2 << 8, /* right justified */
80 AIC26_DATFM_LEFTJ = 3 << 8, /* left justified */
H A Drk817_codec.c1 // SPDX-License-Identifier: GPL-2.0
33 * I don't have another implementation to compare from the Rockchip sources. Hard-coding for now.
46 if (rk817->mic_in_differential) { in rk817_init()
62 /* Set the PLL pre-divide value (values not documented). */ in rk817_set_component_pll()
74 * 0db~-95db, 0.375db/step, for example:
76 * 0xff: -95dB
79 static const DECLARE_TLV_DB_MINMAX(rk817_vol_tlv, -9500, 0);
83 * 27db~-18db, 3db/step, for example:
84 * 0x0: -18dB
88 static const DECLARE_TLV_DB_MINMAX(rk817_gain_tlv, -1800, 2700);
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/openbmc/linux/drivers/gpu/drm/i915/
H A DTODO.txt2 -----------------
4 - For discrete memory manager, merge enough dg1 to be able to refactor it to
8 - Come up with a plan what to do with drm/scheduler and how to get there.
10 - Roll out dma_fence critical section annotations.
12 - There's a lot of complexity added past few years to make relocations faster.
15 1. Land a modern pre-bound uapi like VM_BIND
16 2. Any complexity added in this area past few years which can't be justified
23 - i915_sw_fence seems to be the main structure for the i915-gem dma_fence model.
24 How-to-dma_fence is core and drivers really shouldn't build their own world
27 removed if dri-devel consensus is that it's not a good idea. Once that's done
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/openbmc/linux/include/sound/sof/
H A Ddai.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
13 #include <sound/sof/dai-intel.h>
14 #include <sound/sof/dai-imx.h>
15 #include <sound/sof/dai-amd.h>
16 #include <sound/sof/dai-mediatek.h>
25 #define SOF_DAI_FMT_RIGHT_J 2 /**< Right Justified mode */
26 #define SOF_DAI_FMT_LEFT_J 3 /**< Left Justified mode */
96 uint32_t type; /**< DAI type - enum sof_ipc_dai_type */
/openbmc/linux/arch/parisc/math-emu/
H A Dfpbits.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
10 PA header file -- do not include this header file for non-PA builds.
18 * and bitfield assignment (default left-to-right, unlike VAX, PDP-11)
20 * the C compiler "-D" flag (e.g., -DHOSTWDSZ=36 -DBITFLR for the DEC-20).
22 * is a 32-bit integer (right-justified on the 20) and that bit 0 is the
33 /*-------------------------------------------------------------------------
34 * NewDeclareBitField_Reference - Declare a structure similar to the simulator
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/openbmc/linux/sound/soc/meson/
H A Daxg-tdmout.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <sound/soc-dai.h>
12 #include "axg-tdm-formatter.h"
62 if (!p->connect) in axg_tdmout_get_be()
65 if (p->sink->id == snd_soc_dapm_dai_in) in axg_tdmout_get_be()
66 return (struct snd_soc_dai *)p->sink->priv; in axg_tdmout_get_be()
68 be = axg_tdmout_get_be(p->sink); in axg_tdmout_get_be()
113 unsigned int val, skew = quirks->skew_offset; in axg_tdmout_prepare()
116 switch (ts->iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { in axg_tdmout_prepare()
128 ts->iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK); in axg_tdmout_prepare()
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H A Daxg-toddr.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
15 #include <sound/soc-dai.h>
17 #include "axg-fifo.h"
43 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
47 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
65 type = 2; /* 4 samples of 16 bits - right justified */ in axg_toddr_dai_hw_params()
68 type = 4; /* 2 samples of 32 bits - right justified */ in axg_toddr_dai_hw_params()
71 return -EINVAL; in axg_toddr_dai_hw_params()
76 regmap_update_bits(fifo->map, FIFO_CTRL0, in axg_toddr_dai_hw_params()
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H A Daxg-spdifout.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <sound/soc-dai.h>
97 axg_spdifout_enable(priv->map); in axg_spdifout_trigger()
103 axg_spdifout_disable(priv->map); in axg_spdifout_trigger()
107 return -EINVAL; in axg_spdifout_trigger()
116 regmap_update_bits(priv->map, SPDIFOUT_CTRL0, SPDIFOUT_CTRL0_VSET, in axg_spdifout_mute()
137 dev_err(dai->dev, "too many channels for spdif dai: %u\n", in axg_spdifout_sample_fmt()
139 return -EINVAL; in axg_spdifout_sample_fmt()
142 regmap_update_bits(priv->map, SPDIFOUT_CTRL0, in axg_spdifout_sample_fmt()
152 /* 4 samples of 16 bits - right justified */ in axg_spdifout_sample_fmt()
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/openbmc/linux/arch/s390/include/uapi/asm/
H A Dzcrypt.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
3 * include/asm-s390/zcrypt.h
5 * zcrypt 2.2.1 (user-visible header)
32 * - outputdatalength is at least as large as inputdatalength.
33 * - All key parts are right justified in their fields, padded on
35 * - length(b_key) = inputdatalength
36 * - length(n_modulus) = inputdatalength
51 * - inputdatalength is even.
52 * - outputdatalength is at least as large as inputdatalength.
53 * - All key parts are right justified in their fields, padded on
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/openbmc/linux/sound/soc/au1x/
H A Di2sc.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <asm/mach-au1x00/au1000.h>
40 #define CFG_FM_LJ (1 << 7) /* left-justified */
41 #define CFG_FM_RJ (2 << 7) /* right-justified */
72 return __raw_readl(ctx->mmio + reg); in RD()
77 __raw_writel(v, ctx->mmio + reg); in WR()
87 ret = -EINVAL; in au1xi2s_set_fmt()
88 c = ctx->cfg; in au1xi2s_set_fmt()
105 c &= ~(CFG_IC | CFG_ICK); /* IB-IF */ in au1xi2s_set_fmt()
131 ctx->cfg = c; in au1xi2s_set_fmt()
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