| /openbmc/linux/include/linux/mmc/ |
| H A D | host.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #include <linux/fault-inject.h>
17 #include <linux/dma-direction.h>
18 #include <linux/blk-crypto-profile.h>
141 * ios->clock might be 0. For some controllers, setting 0Hz
151 * 1 for a read-only card
152 * -ENOSYS when not supported (equal to NULL callback)
161 * -ENOSYS when not supported (equal to NULL callback)
178 /* The tuning command opcode value is different for SD and eMMC cards */
184 /* Execute HS400 tuning depending host driver */
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | sdhci-xenon.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
22 #include "sdhci-pltfm.h"
23 #include "sdhci-xenon.h"
42 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); in xenon_enable_internal_clk()
43 return -ETIMEDOUT; in xenon_enable_internal_clk()
51 /* Set SDCLK-off-while-idle */
92 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in xenon_enable_sdhc()
97 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; in xenon_enable_sdhc()
138 /* Disable the Re-Tuning Request functionality */ in xenon_retune_setup()
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| H A D | sdhci-esdhc-imx.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
23 #include <linux/mmc/slot-gpio.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
30 #include "sdhci-esdhc.h"
70 /* Tuning bits */
82 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
106 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
140 * open ended multi-blk IO. Otherwise the TC INT wouldn't
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| H A D | renesas_sdhi_core.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
13 * Copyright 2004-2005 Phil Blundell
14 * Copyright 2007-2008 OpenedHand Ltd.
28 #include <linux/mmc/slot-gpio.h>
31 #include <linux/pinctrl/pinctrl-state.h>
95 struct mmc_host *mmc = host->mmc; in renesas_sdhi_clk_enable()
99 ret = clk_prepare_enable(priv->clk_cd); in renesas_sdhi_clk_enable()
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| H A D | sdhci.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
103 * VDD2 - UHS2 or PCIe/NVMe
174 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
196 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
243 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
252 /* 4C-4F reserved for more max current */
259 /* 55-57 reserved */
264 /* 60-FB reserved */
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| H A D | sdhci-of-esdhc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
22 #include <linux/dma-mapping.h>
26 #include "sdhci-pltfm.h"
27 #include "sdhci-esdhc.h"
71 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
72 { .compatible = "fsl,ls1043a-esdhc", .data = &ls1043a_esdhc_clk},
73 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
74 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
75 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
76 { .compatible = "fsl,mpc8379-esdhc" },
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| H A D | sdhci-acpi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/pinctrl/pinconf-generic.h>
17 #include <linux/dma-mapping.h>
32 #include <linux/mmc/slot-gpio.h>
90 return (void *)c->private; in sdhci_acpi_priv()
95 return c->slot && (c->slot->flags & flag); in sdhci_acpi_flag()
127 return -EOPNOTSUPP; in __intel_dsm()
129 if (obj->type == ACPI_TYPE_INTEGER) { in __intel_dsm()
130 *result = obj->integer.value; in __intel_dsm()
131 } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) { in __intel_dsm()
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| H A D | sdhci-xenon-phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
17 #include "sdhci-pltfm.h"
18 #include "sdhci-xenon.h"
197 /* Divider for calculating Tuning Step */
209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
211 return -ENOMEM; in xenon_alloc_emmc_phy()
213 priv->phy_params = params; in xenon_alloc_emmc_phy()
214 if (priv->phy_type == EMMC_5_0_PHY) in xenon_alloc_emmc_phy()
215 priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs; in xenon_alloc_emmc_phy()
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| /openbmc/phosphor-pid-control/ |
| H A D | main.cpp | 8 * http://www.apache.org/licenses/LICENSE-2.0
27 #include "pid/tuning.hpp"
116 timer->cancel(); in stopControlLoops()
121 if (state::zones.size() > 0 && state::zones.begin()->second.use_count() > 1) in stopControlLoops()
221 // re-try control loop, set up a delay. in tryRestartControlLoops()
262 // re-try control loop, set up a delay. in tryTerminateControlLoops()
316 app.add_option("-c,--conf", configPath, in main()
317 "Optional parameter to specify configuration at run-time") in main()
318 ->check(CLI::ExistingFile); in main()
319 app.add_option("-l,--log", loggingPath, in main()
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| /openbmc/linux/Documentation/admin-guide/sysctl/ |
| H A D | index.rst | 7 ------------------------------------------------------------------------------
18 be actually used, not just for the fun of programming it :-)
20 ------------------------------------------------------------------------------
37 you're the last RTFMing person to screw up.
39 In short, e-mail your suggestions, corrections and / or horror
44 --------------------------------------------------------------
50 at run-time, and the /proc/sys/ directory is there so that you
55 - a running Linux system
56 - root access
57 - common sense (this is especially hard to come by these days)
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| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | marvell,xenon-sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
29 - items:
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | renesas-sdhi.c | 1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-direction.h>
18 #include "tmio-common.h"
116 bool hs400 = (mmc->selected_mode == MMC_HS_400); in renesas_sdhi_hs400()
117 int ret, taps = hs400 ? priv->nrtaps : 8; in renesas_sdhi_hs400()
121 ret = clk_set_rate(&priv->clk, 400000000); in renesas_sdhi_hs400()
123 ret = clk_set_rate(&priv->clk, 200000000); in renesas_sdhi_hs400()
145 tmio_sd_writel(priv, priv->tap_set >> 1, in renesas_sdhi_hs400()
148 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET); in renesas_sdhi_hs400()
182 unsigned long tap_cnt; /* counter of tuning success */ in renesas_sdhi_select_tuning()
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| H A D | xenon_sdhci.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * Date: 2016-8-24
13 * Ported to from Marvell 2015.01 to mainline U-Boot 2017.01:
26 /* Register Offset of SD Host Controller SOCP self-defined register */
133 struct xenon_sdhci_priv *priv = host->mmc->priv; in xenon_mmc_phy_init()
134 u32 clock = priv->clock; in xenon_mmc_phy_init()
141 if ((priv->timing == MMC_TIMING_UHS_SDR50) || in xenon_mmc_phy_init()
142 (priv->timing == MMC_TIMING_UHS_SDR25) || in xenon_mmc_phy_init()
143 (priv->timing == MMC_TIMING_UHS_SDR12) || in xenon_mmc_phy_init()
144 (priv->timing == MMC_TIMING_SD_HS) || in xenon_mmc_phy_init()
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| /openbmc/linux/Documentation/admin-guide/media/ |
| H A D | bt8xx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
16 -------------------
21 Please see Documentation/admin-guide/media/bttv-cardlist.rst for a complete
28 ./scripts/config -e PCI
29 ./scripts/config -e INPUT
30 ./scripts/config -m I2C
31 ./scripts/config -m MEDIA_SUPPORT
32 ./scripts/config -e MEDIA_PCI_SUPPORT
33 ./scripts/config -e MEDIA_ANALOG_TV_SUPPORT
34 ./scripts/config -e MEDIA_DIGITAL_TV_SUPPORT
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| H A D | faq.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 avoid confusion, we're calling *transponders* as the physical
23 1. The signal seems to die a few seconds after tuning.
28 is closed). The ``dvb-core`` module parameter ``dvb_shutdown_timeout``
37 tools and are grouped together with the ``v4l-utils`` git repository:
39 https://git.linuxtv.org/v4l-utils.git/
48 for example the ``dvbv5-scan`` tool. You can find more information
51 https://www.linuxtv.org/wiki/index.php/Dvbv5-scan
70 https://git.linuxtv.org/dtv-scan-tables.git
88 list with a tool like ``dvbv5-scan``.
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| /openbmc/linux/drivers/media/dvb-core/ |
| H A D | dvb_frontend.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dvb_frontend.c: DVB frontend tuning interface/thread
5 * Copyright (C) 1999-2001 Ralph Metzler
10 * Copyright (C) 2004 Andrew de Quincey (tuning thread cleanup)
57 MODULE_PARM_DESC(dvb_mfe_wait_time, "Wait up to <mfe_wait_time> seconds on open() for multi-fronten…
77 * FESTATE_IDLE. No tuning parameters have been supplied and the loop is idling.
79 * FESTATE_TUNING_FAST. Tuning parameters have been supplied and fast zigzag scan is in progress.
80 …* FESTATE_TUNING_SLOW. Tuning parameters have been supplied. Fast zigzag failed, so we're trying a…
83 …* FESTATE_ZIGZAG_SLOW. The lock has been lost. Fast zigzag has been failed, so we're trying again,…
85 * FESTATE_WAITFORLOCK. When we're waiting for a lock.
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| /openbmc/linux/Documentation/driver-api/media/ |
| H A D | dtv-frontend.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ------------------------
9 The Digital TV Frontend kABI defines a driver-internal interface for
10 registering low-level, hardware specific driver to a hardware independent
29 .name = "foo DVB-T/T2/C driver",
70 .name = "Bar DVB-S/S2 demodulator",
91 /* Satellite-specific */
100 #) For satellite digital TV standards (DVB-S, DVB-S2, ISDB-S), the
102 standards, they're specified in Hz. Due to that, if the same frontend
124 responsible for tuning the device. It supports multiple algorithms to
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| /openbmc/u-boot/board/varisys/cyrus/ |
| H A D | eth.c | 1 // SPDX-License-Identifier: GPL-2.0+
36 printf("Tuning PHY @ %d\n", phy); in cyrus_phy_tuning()
40 /* Sets RXC/TXC to +0.96ns and TX_CTL/RX_CTL to -0.84ns */ in cyrus_phy_tuning()
44 /* writes to address 0x105 , RXD[3..0] to -0. */ in cyrus_phy_tuning()
48 /* writes to address 0x106 , TXD[3..0] to -0.84ns */ in cyrus_phy_tuning()
50 /* force re-negotiation */ in cyrus_phy_tuning()
79 /* Never disable DTSEC1 - it controls MDIO */ in board_eth_init()
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| /openbmc/linux/drivers/clk/rockchip/ |
| H A D | clk-mmc-phase.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
58 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
94 * for people to debug unstable mmc tuning results. in rockchip_mmc_set_phase()
98 return -EINVAL; in rockchip_mmc_set_phase()
106 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
119 * degrees off from what we think we're making. That's OK in rockchip_mmc_set_phase()
125 * don't overflow 32-bit / 64-bit numbers. in rockchip_mmc_set_phase()
138 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), in rockchip_mmc_set_phase()
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| /openbmc/openbmc/poky/meta/classes-global/ |
| H A D | sanity.bbclass | 4 # SPDX-License-Identifier: MIT
23 import re
26 if re.search(pattern, line)), (None, None))
43 SANITY_DIFF_TOOL ?= "diff -u"
115 if start != -1 and (len(bbpath_line) != (start + 1)):
147 # Handle rename of meta-yocto -> meta-poky
148 # This marks the start of separate version numbers but code is needed in OE-Core
152 if 'meta-yocto' in layers:
155 index, meta_yocto_line = sanity_conf_find_line(r'.*meta-yocto[\'"\s\n]', lines)
157 lines[index] = meta_yocto_line.replace('meta-yocto', 'meta-poky')
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| /openbmc/openbmc/poky/documentation/migration-guides/ |
| H A D | migration-2.1.rst | 1 .. SPDX-License-Identifier: CC-BY-SA-2.0-UK
9 .. _migration-2.1-variable-expansion-in-python-functions:
12 --------------------------------------
23 .. _migration-2.1-overrides-must-now-be-lower-case:
25 Overrides Must Now be Lower-Case
26 --------------------------------
28 The convention for overrides has always been for them to be lower-case
30 now assumes lower-case characters in order to give a slight performance
33 appear in lower-case characters (e.g. values for :term:`MACHINE`,
35 ``_pn-``\ recipename overrides are to be effective).
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| /openbmc/linux/include/media/ |
| H A D | tuner-types.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * enum param_type - type of the tuner pameters
27 * struct tuner_range - define the frequencies supported by the tuner
36 * those ranges, as they're defined inside the driver. This is used by
54 * struct tuner_params - Parameters to be used to setup the tuner. Those
55 * are used by drivers/media/tuners/tuner-types.c in
57 * the parameters are for tuners based on tda9887 IF-PLL
58 * multi-standard analog TV/Radio demodulator, with is
65 * @cb_first_if_lower_freq: Many Philips-based tuners have a comment in
68 * switching, and to ensure smooth tuning to the
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| /openbmc/openbmc/poky/meta/conf/machine/include/microblaze/ |
| H A D | arch-microblaze.inc | 7 # 64-bit
8 TUNEVALID[64-bit] = "64-bit MicroBlaze"
9 TUNECONFLICTS[64-bit] = "v8.00 v8.10 v8.20 v8.30 v8.40 v8.50 v9.0 v9.1 v9.2 v9.3 v9.4 v9.5 v9.6 v10…
10 MACHINEOVERRIDES =. "${@bb.utils.contains("TUNE_FEATURES", "64-bit", "microblaze64:", "", d)}"
18 TUNE_CCARGS .= "${@bb.utils.contains("TUNE_FEATURES", "bigendian", " -mbig-endian", " -mlittle-endi…
21 TUNEVALID[barrel-shift] = "Enable Hardware Barrel Shifter"
22 TUNEVALID[pattern-compare] = "Enable Pattern Compare Instructions"
27 TUNEVALID[frequency-optimized] = "Enabling tuning for frequency optimized core (AREA_OPTIMIZED_2)"
28 TUNECONFLICTS[frequency-optimized] = "v8.00 v8.10 v8.20 v8.30 v8.40 v8.50 v9.0 v9.1 v9.2 v9.3 v9.4 …
31 …GS .= "${@bb.utils.contains("TUNE_FEATURES", "barrel-shift", " -mxl-barrel-shift", " -mno-xl-barre…
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| /openbmc/linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-emmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
20 * The higher 16-bit of this register is used for write protection
106 regmap_write(rk_phy->reg_base, in rockchip_emmc_phy_power()
107 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
111 regmap_write(rk_phy->reg_base, in rockchip_emmc_phy_power()
112 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
121 rate = clk_get_rate(rk_phy->emmcclk); in rockchip_emmc_phy_power()
146 rate - ideal_rate : ideal_rate - rate; in rockchip_emmc_phy_power()
149 * In order for tuning delays to be accurate we need to be in rockchip_emmc_phy_power()
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| /openbmc/u-boot/arch/arm/mach-orion5x/ |
| H A D | lowlevel_init.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
23 /* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
36 * For Guideline MEM-3 - Drive Strength value
43 * For Guideline MEM-4 - DQS Reference Delay Tuning
62 * Low-level init happens right after start.S has switched to SVC32,
63 * flushed and disabled caches and disabled MMU. We're still running
65 * set up the RAM to copy U-Boot into.
213 /* Implement Guideline (GL# MEM-3) Drive Strength Value */
214 /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
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