1f707079dSWolfram Sang // SPDX-License-Identifier: GPL-2.0
2b5b6a5f4SSimon Horman /*
39d08428aSSimon Horman * Renesas SDHI
4b5b6a5f4SSimon Horman *
5f49bdcdeSWolfram Sang * Copyright (C) 2015-19 Renesas Electronics Corporation
6f49bdcdeSWolfram Sang * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
787317c4dSSimon Horman * Copyright (C) 2016-17 Horms Solutions, Simon Horman
8b5b6a5f4SSimon Horman * Copyright (C) 2009 Magnus Damm
9b5b6a5f4SSimon Horman *
10b5b6a5f4SSimon Horman * Based on "Compaq ASIC3 support":
11b5b6a5f4SSimon Horman *
12b5b6a5f4SSimon Horman * Copyright 2001 Compaq Computer Corporation.
13b5b6a5f4SSimon Horman * Copyright 2004-2005 Phil Blundell
14b5b6a5f4SSimon Horman * Copyright 2007-2008 OpenedHand Ltd.
15b5b6a5f4SSimon Horman *
16b5b6a5f4SSimon Horman * Authors: Phil Blundell <pb@handhelds.org>,
17b5b6a5f4SSimon Horman * Samuel Ortiz <sameo@openedhand.com>
18b5b6a5f4SSimon Horman *
19b5b6a5f4SSimon Horman */
20b5b6a5f4SSimon Horman
21b5b6a5f4SSimon Horman #include <linux/clk.h>
22ab07a135SWolfram Sang #include <linux/delay.h>
23b4d86f37SWolfram Sang #include <linux/iopoll.h>
24ab07a135SWolfram Sang #include <linux/kernel.h>
25ab07a135SWolfram Sang #include <linux/mfd/tmio.h>
26b5b6a5f4SSimon Horman #include <linux/mmc/host.h>
27ce6f92c2SWolfram Sang #include <linux/mmc/mmc.h>
28ef5332c1SWolfram Sang #include <linux/mmc/slot-gpio.h>
29ab07a135SWolfram Sang #include <linux/module.h>
30b5b6a5f4SSimon Horman #include <linux/pinctrl/consumer.h>
31b5b6a5f4SSimon Horman #include <linux/pinctrl/pinctrl-state.h>
32ab07a135SWolfram Sang #include <linux/platform_device.h>
33ab07a135SWolfram Sang #include <linux/pm_domain.h>
34b5b6a5f4SSimon Horman #include <linux/regulator/consumer.h>
35b4d86f37SWolfram Sang #include <linux/reset.h>
36ab07a135SWolfram Sang #include <linux/sh_dma.h>
37ab07a135SWolfram Sang #include <linux/slab.h>
38b5b6a5f4SSimon Horman
39b5b6a5f4SSimon Horman #include "renesas_sdhi.h"
40b5b6a5f4SSimon Horman #include "tmio_mmc.h"
41b5b6a5f4SSimon Horman
424533c3ebSWolfram Sang #define CTL_HOST_MODE 0xe4
434533c3ebSWolfram Sang #define HOST_MODE_GEN2_SDR50_WMODE BIT(0)
444533c3ebSWolfram Sang #define HOST_MODE_GEN2_SDR104_WMODE BIT(0)
454533c3ebSWolfram Sang #define HOST_MODE_GEN3_WMODE BIT(0)
464533c3ebSWolfram Sang #define HOST_MODE_GEN3_BUSWIDTH BIT(8)
474533c3ebSWolfram Sang
484533c3ebSWolfram Sang #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE
494533c3ebSWolfram Sang #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH)
504533c3ebSWolfram Sang #define HOST_MODE_GEN3_64BIT 0
51b5b6a5f4SSimon Horman
52b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR50 0x490c
53c7825151SWolfram Sang #define SDHI_VER_RZ_A1 0x820b
54b5b6a5f4SSimon Horman /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
55b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR104 0xcb0d
56b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SD 0xcc10
57b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SDMMC 0xcd10
58b5b6a5f4SSimon Horman
59ce6f92c2SWolfram Sang #define SDHI_GEN3_MMC0_ADDR 0xee140000
60ce6f92c2SWolfram Sang
renesas_sdhi_sdbuf_width(struct tmio_mmc_host * host,int width)61b5b6a5f4SSimon Horman static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
62b5b6a5f4SSimon Horman {
63b5b6a5f4SSimon Horman u32 val;
64b5b6a5f4SSimon Horman
65b5b6a5f4SSimon Horman /*
66b5b6a5f4SSimon Horman * see also
67b5b6a5f4SSimon Horman * renesas_sdhi_of_data :: dma_buswidth
68b5b6a5f4SSimon Horman */
69b5b6a5f4SSimon Horman switch (sd_ctrl_read16(host, CTL_VERSION)) {
70b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR50:
714533c3ebSWolfram Sang val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0;
72b5b6a5f4SSimon Horman break;
73b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR104:
744533c3ebSWolfram Sang val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE;
75b5b6a5f4SSimon Horman break;
76b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SD:
77b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SDMMC:
78b5b6a5f4SSimon Horman if (width == 64)
794533c3ebSWolfram Sang val = HOST_MODE_GEN3_64BIT;
80b5b6a5f4SSimon Horman else if (width == 32)
814533c3ebSWolfram Sang val = HOST_MODE_GEN3_32BIT;
82b5b6a5f4SSimon Horman else
834533c3ebSWolfram Sang val = HOST_MODE_GEN3_16BIT;
84b5b6a5f4SSimon Horman break;
85b5b6a5f4SSimon Horman default:
86b5b6a5f4SSimon Horman /* nothing to do */
87b5b6a5f4SSimon Horman return;
88b5b6a5f4SSimon Horman }
89b5b6a5f4SSimon Horman
904533c3ebSWolfram Sang sd_ctrl_write16(host, CTL_HOST_MODE, val);
91b5b6a5f4SSimon Horman }
92b5b6a5f4SSimon Horman
renesas_sdhi_clk_enable(struct tmio_mmc_host * host)93b5b6a5f4SSimon Horman static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
94b5b6a5f4SSimon Horman {
95b5b6a5f4SSimon Horman struct mmc_host *mmc = host->mmc;
96b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host);
97d42c9fffSWolfram Sang int ret;
98b5b6a5f4SSimon Horman
99b5b6a5f4SSimon Horman ret = clk_prepare_enable(priv->clk_cd);
100d42c9fffSWolfram Sang if (ret < 0)
101b5b6a5f4SSimon Horman return ret;
102b5b6a5f4SSimon Horman
103b5b6a5f4SSimon Horman /*
104b5b6a5f4SSimon Horman * The clock driver may not know what maximum frequency
105b5b6a5f4SSimon Horman * actually works, so it should be set with the max-frequency
106b5b6a5f4SSimon Horman * property which will already have been read to f_max. If it
107b5b6a5f4SSimon Horman * was missing, assume the current frequency is the maximum.
108b5b6a5f4SSimon Horman */
109b5b6a5f4SSimon Horman if (!mmc->f_max)
110b5b6a5f4SSimon Horman mmc->f_max = clk_get_rate(priv->clk);
111b5b6a5f4SSimon Horman
112b5b6a5f4SSimon Horman /*
113b5b6a5f4SSimon Horman * Minimum frequency is the minimum input clock frequency
114b5b6a5f4SSimon Horman * divided by our maximum divider.
115b5b6a5f4SSimon Horman */
116b5b6a5f4SSimon Horman mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
117b5b6a5f4SSimon Horman
118b5b6a5f4SSimon Horman /* enable 16bit data access on SDBUF as default */
119b5b6a5f4SSimon Horman renesas_sdhi_sdbuf_width(host, 16);
120b5b6a5f4SSimon Horman
121b5b6a5f4SSimon Horman return 0;
122b5b6a5f4SSimon Horman }
123b5b6a5f4SSimon Horman
renesas_sdhi_clk_update(struct tmio_mmc_host * host,unsigned int wanted_clock)124b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
125bb6d3fa9SWolfram Sang unsigned int wanted_clock)
126b5b6a5f4SSimon Horman {
127b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host);
128bb6d3fa9SWolfram Sang struct clk *ref_clk = priv->clk;
129b5b6a5f4SSimon Horman unsigned int freq, diff, best_freq = 0, diff_min = ~0;
130bb6d3fa9SWolfram Sang unsigned int new_clock, clkh_shift = 0;
131f0c00454SBiju Das unsigned int new_upper_limit;
13275eaf49fSTamás Szűcs int i;
133b5b6a5f4SSimon Horman
1340f93db65SWolfram Sang /*
1350f93db65SWolfram Sang * We simply return the current rate if a) we are not on a R-Car Gen2+
1360f93db65SWolfram Sang * SoC (may work for others, but untested) or b) if the SCC needs its
1370f93db65SWolfram Sang * clock during tuning, so we don't change the external clock setup.
1380f93db65SWolfram Sang */
1390f93db65SWolfram Sang if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
140b5b6a5f4SSimon Horman return clk_get_rate(priv->clk);
141b5b6a5f4SSimon Horman
142bb6d3fa9SWolfram Sang if (priv->clkh) {
14346d4820fSWolfram Sang /* HS400 with 4TAP needs different clock settings */
14448c917faSWolfram Sang bool use_4tap = sdhi_has_quirk(priv, hs400_4taps);
14546d4820fSWolfram Sang bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400;
146bb6d3fa9SWolfram Sang clkh_shift = use_4tap && need_slow_clkh ? 1 : 2;
147bb6d3fa9SWolfram Sang ref_clk = priv->clkh;
148bb6d3fa9SWolfram Sang }
149bb6d3fa9SWolfram Sang
150bb6d3fa9SWolfram Sang new_clock = wanted_clock << clkh_shift;
151bb6d3fa9SWolfram Sang
152b5b6a5f4SSimon Horman /*
153b5b6a5f4SSimon Horman * We want the bus clock to be as close as possible to, but no
154b5b6a5f4SSimon Horman * greater than, new_clock. As we can divide by 1 << i for
155b5b6a5f4SSimon Horman * any i in [0, 9] we want the input clock to be as close as
156b5b6a5f4SSimon Horman * possible, but no greater than, new_clock << i.
157f0c00454SBiju Das *
158f0c00454SBiju Das * Add an upper limit of 1/1024 rate higher to the clock rate to fix
159f0c00454SBiju Das * clk rate jumping to lower rate due to rounding error (eg: RZ/G2L has
160f0c00454SBiju Das * 3 clk sources 533.333333 MHz, 400 MHz and 266.666666 MHz. The request
161f0c00454SBiju Das * for 533.333333 MHz will selects a slower 400 MHz due to rounding
162f0c00454SBiju Das * error (533333333 Hz / 4 * 4 = 533333332 Hz < 533333333 Hz)).
163b5b6a5f4SSimon Horman */
164b5b6a5f4SSimon Horman for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
165bb6d3fa9SWolfram Sang freq = clk_round_rate(ref_clk, new_clock << i);
166f0c00454SBiju Das new_upper_limit = (new_clock << i) + ((new_clock << i) >> 10);
167f0c00454SBiju Das if (freq > new_upper_limit) {
168b5b6a5f4SSimon Horman /* Too fast; look for a slightly slower option */
169bb6d3fa9SWolfram Sang freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3);
170f0c00454SBiju Das if (freq > new_upper_limit)
171b5b6a5f4SSimon Horman continue;
172b5b6a5f4SSimon Horman }
173b5b6a5f4SSimon Horman
174b5b6a5f4SSimon Horman diff = new_clock - (freq >> i);
175b5b6a5f4SSimon Horman if (diff <= diff_min) {
176b5b6a5f4SSimon Horman best_freq = freq;
177b5b6a5f4SSimon Horman diff_min = diff;
178b5b6a5f4SSimon Horman }
179b5b6a5f4SSimon Horman }
180b5b6a5f4SSimon Horman
181bb6d3fa9SWolfram Sang clk_set_rate(ref_clk, best_freq);
182bb6d3fa9SWolfram Sang
183bb6d3fa9SWolfram Sang if (priv->clkh)
184bb6d3fa9SWolfram Sang clk_set_rate(priv->clk, best_freq >> clkh_shift);
185b5b6a5f4SSimon Horman
18675eaf49fSTamás Szűcs return clk_get_rate(priv->clk);
187b5b6a5f4SSimon Horman }
188b5b6a5f4SSimon Horman
renesas_sdhi_set_clock(struct tmio_mmc_host * host,unsigned int new_clock)1890196c8dbSMasahiro Yamada static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
1900196c8dbSMasahiro Yamada unsigned int new_clock)
1910196c8dbSMasahiro Yamada {
192f0c00454SBiju Das unsigned int clk_margin;
1930196c8dbSMasahiro Yamada u32 clk = 0, clock;
1940196c8dbSMasahiro Yamada
19568f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
19668f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
19768f83127SMasahiro Yamada
19875eaf49fSTamás Szűcs if (new_clock == 0) {
19975eaf49fSTamás Szűcs host->mmc->actual_clock = 0;
20068f83127SMasahiro Yamada goto out;
20175eaf49fSTamás Szűcs }
20268f83127SMasahiro Yamada
20375eaf49fSTamás Szűcs host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
20475eaf49fSTamás Szűcs clock = host->mmc->actual_clock / 512;
2050196c8dbSMasahiro Yamada
206f0c00454SBiju Das /*
207f0c00454SBiju Das * Add a margin of 1/1024 rate higher to the clock rate in order
208f0c00454SBiju Das * to avoid clk variable setting a value of 0 due to the margin
209f0c00454SBiju Das * provided for actual_clock in renesas_sdhi_clk_update().
210f0c00454SBiju Das */
211f0c00454SBiju Das clk_margin = new_clock >> 10;
212f0c00454SBiju Das for (clk = 0x80000080; new_clock + clk_margin >= (clock << 1); clk >>= 1)
2130196c8dbSMasahiro Yamada clock <<= 1;
2140196c8dbSMasahiro Yamada
2150196c8dbSMasahiro Yamada /* 1/1 clock is option */
2160196c8dbSMasahiro Yamada if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
2170196c8dbSMasahiro Yamada if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
2180196c8dbSMasahiro Yamada clk |= 0xff;
2190196c8dbSMasahiro Yamada else
2200196c8dbSMasahiro Yamada clk &= ~0xff;
2210196c8dbSMasahiro Yamada }
2220196c8dbSMasahiro Yamada
2230196c8dbSMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
2240196c8dbSMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
2250196c8dbSMasahiro Yamada usleep_range(10000, 11000);
2260196c8dbSMasahiro Yamada
22768f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
22868f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
22968f83127SMasahiro Yamada
23068f83127SMasahiro Yamada out:
23168f83127SMasahiro Yamada /* HW engineers overrode docs: no sleep needed on R-Car2+ */
23268f83127SMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
23368f83127SMasahiro Yamada usleep_range(10000, 11000);
2340196c8dbSMasahiro Yamada }
2350196c8dbSMasahiro Yamada
renesas_sdhi_clk_disable(struct tmio_mmc_host * host)236b5b6a5f4SSimon Horman static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
237b5b6a5f4SSimon Horman {
238b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host);
239b5b6a5f4SSimon Horman
240b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk_cd);
241b5b6a5f4SSimon Horman }
242b5b6a5f4SSimon Horman
renesas_sdhi_card_busy(struct mmc_host * mmc)243b5b6a5f4SSimon Horman static int renesas_sdhi_card_busy(struct mmc_host *mmc)
244b5b6a5f4SSimon Horman {
245b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc);
246b5b6a5f4SSimon Horman
2472fe35968SSimon Horman return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
2482fe35968SSimon Horman TMIO_STAT_DAT0);
249b5b6a5f4SSimon Horman }
250b5b6a5f4SSimon Horman
renesas_sdhi_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)251b5b6a5f4SSimon Horman static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
252b5b6a5f4SSimon Horman struct mmc_ios *ios)
253b5b6a5f4SSimon Horman {
254b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc);
255b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host);
256b5b6a5f4SSimon Horman struct pinctrl_state *pin_state;
257b5b6a5f4SSimon Horman int ret;
258b5b6a5f4SSimon Horman
259b5b6a5f4SSimon Horman switch (ios->signal_voltage) {
260b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_330:
261b5b6a5f4SSimon Horman pin_state = priv->pins_default;
262b5b6a5f4SSimon Horman break;
263b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_180:
264b5b6a5f4SSimon Horman pin_state = priv->pins_uhs;
265b5b6a5f4SSimon Horman break;
266b5b6a5f4SSimon Horman default:
267b5b6a5f4SSimon Horman return -EINVAL;
268b5b6a5f4SSimon Horman }
269b5b6a5f4SSimon Horman
270b5b6a5f4SSimon Horman /*
271b5b6a5f4SSimon Horman * If anything is missing, assume signal voltage is fixed at
272b5b6a5f4SSimon Horman * 3.3V and succeed/fail accordingly.
273b5b6a5f4SSimon Horman */
274b5b6a5f4SSimon Horman if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
275b5b6a5f4SSimon Horman return ios->signal_voltage ==
276b5b6a5f4SSimon Horman MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
277b5b6a5f4SSimon Horman
278b5b6a5f4SSimon Horman ret = mmc_regulator_set_vqmmc(host->mmc, ios);
2799cbe0fc8SMarek Vasut if (ret < 0)
280b5b6a5f4SSimon Horman return ret;
281b5b6a5f4SSimon Horman
282b5b6a5f4SSimon Horman return pinctrl_select_state(priv->pinctrl, pin_state);
283b5b6a5f4SSimon Horman }
284b5b6a5f4SSimon Horman
285b5b6a5f4SSimon Horman /* SCC registers */
286b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
287b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_TAPSET 0x002
288b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DT2FF 0x004
289b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL 0x006
290b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
291b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
29271cfc927STakeshi Saito #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C
29326eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
294ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014
295ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016
296ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018
297ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A
298ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C
299b5b6a5f4SSimon Horman
300b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
301b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
302b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
303b5b6a5f4SSimon Horman
304b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
3056199a10eSWolfram Sang
306b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
3076199a10eSWolfram Sang
30811a21960STakeshi Saito #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
3096199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
3106199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
3116199a10eSWolfram Sang
31271cfc927STakeshi Saito #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
3136199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
3146199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24))
3156199a10eSWolfram Sang
31626eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
31726eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
318b5b6a5f4SSimon Horman
319ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */
320ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
321ce6f92c2SWolfram Sang
322ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */
323ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
324ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
325ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
326ce6f92c2SWolfram Sang
327ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC register */
328ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
329ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
330ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
331ce6f92c2SWolfram Sang
sd_scc_read32(struct tmio_mmc_host * host,struct renesas_sdhi * priv,int addr)332b5b6a5f4SSimon Horman static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
333b5b6a5f4SSimon Horman struct renesas_sdhi *priv, int addr)
334b5b6a5f4SSimon Horman {
335b5b6a5f4SSimon Horman return readl(priv->scc_ctl + (addr << host->bus_shift));
336b5b6a5f4SSimon Horman }
337b5b6a5f4SSimon Horman
sd_scc_write32(struct tmio_mmc_host * host,struct renesas_sdhi * priv,int addr,u32 val)338b5b6a5f4SSimon Horman static inline void sd_scc_write32(struct tmio_mmc_host *host,
339b5b6a5f4SSimon Horman struct renesas_sdhi *priv,
340b5b6a5f4SSimon Horman int addr, u32 val)
341b5b6a5f4SSimon Horman {
342b5b6a5f4SSimon Horman writel(val, priv->scc_ctl + (addr << host->bus_shift));
343b5b6a5f4SSimon Horman }
344b5b6a5f4SSimon Horman
renesas_sdhi_init_tuning(struct tmio_mmc_host * host)345b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
346b5b6a5f4SSimon Horman {
347b5b6a5f4SSimon Horman struct renesas_sdhi *priv;
348b5b6a5f4SSimon Horman
349b5b6a5f4SSimon Horman priv = host_to_priv(host);
350b5b6a5f4SSimon Horman
351b5b6a5f4SSimon Horman /* Initialize SCC */
352b5b6a5f4SSimon Horman sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
353b5b6a5f4SSimon Horman
354b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
355b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
356b5b6a5f4SSimon Horman
35726eb2607SMasaharu Hayakawa /* set sampling clock selection range */
35826eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
35926eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
36026eb2607SMasaharu Hayakawa 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
36126eb2607SMasaharu Hayakawa
362b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
363b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
364b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
365b5b6a5f4SSimon Horman
366b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
367b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
368b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
369b5b6a5f4SSimon Horman
370852d258fSMasahiro Yamada sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
371b5b6a5f4SSimon Horman
37226eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
37326eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
37426eb2607SMasaharu Hayakawa
375b5b6a5f4SSimon Horman /* Read TAPNUM */
376b5b6a5f4SSimon Horman return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
377b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
378b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
379b5b6a5f4SSimon Horman }
380b5b6a5f4SSimon Horman
renesas_sdhi_hs400_complete(struct mmc_host * mmc)381f22084b6SWolfram Sang static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
38226eb2607SMasaharu Hayakawa {
383f22084b6SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc);
38426eb2607SMasaharu Hayakawa struct renesas_sdhi *priv = host_to_priv(host);
385a38c078fSTakeshi Saito u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
38648c917faSWolfram Sang bool use_4tap = sdhi_has_quirk(priv, hs400_4taps);
38726eb2607SMasaharu Hayakawa
38826eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
38926eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
39026eb2607SMasaharu Hayakawa
39126eb2607SMasaharu Hayakawa /* Set HS400 mode */
3920e08a411SWolfram Sang sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 |
39326eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE));
394f0c8234cSTakeshi Saito
395f0c8234cSTakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
396f0c8234cSTakeshi Saito priv->scc_tappos_hs400);
397f0c8234cSTakeshi Saito
39848c917faSWolfram Sang if (sdhi_has_quirk(priv, manual_tap_correction))
3999b0d6855SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
4009b0d6855SWolfram Sang ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
4019b0d6855SWolfram Sang sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
4029b0d6855SWolfram Sang
40326eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
40426eb2607SMasaharu Hayakawa (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
40526eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
40626eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
40726eb2607SMasaharu Hayakawa
40826eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
40926eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
41003e59b1eSWolfram Sang sd_scc_read32(host, priv,
41103e59b1eSWolfram Sang SH_MOBILE_SDHI_SCC_DTCNTL));
41226eb2607SMasaharu Hayakawa
413a38c078fSTakeshi Saito /* Avoid bad TAP */
414a38c078fSTakeshi Saito if (bad_taps & BIT(priv->tap_set)) {
415a38c078fSTakeshi Saito u32 new_tap = (priv->tap_set + 1) % priv->tap_num;
41626eb2607SMasaharu Hayakawa
417a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap))
418a38c078fSTakeshi Saito new_tap = (priv->tap_set - 1) % priv->tap_num;
419a38c078fSTakeshi Saito
420a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap)) {
421a38c078fSTakeshi Saito new_tap = priv->tap_set;
422a38c078fSTakeshi Saito dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n");
423a38c078fSTakeshi Saito }
424a38c078fSTakeshi Saito
425a38c078fSTakeshi Saito priv->tap_set = new_tap;
426a38c078fSTakeshi Saito }
427a38c078fSTakeshi Saito
42826eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
429a38c078fSTakeshi Saito priv->tap_set / (use_4tap ? 2 : 1));
43026eb2607SMasaharu Hayakawa
43126eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
43226eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
43326eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
43426eb2607SMasaharu Hayakawa
43526eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
43626eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
437ce6f92c2SWolfram Sang
438ce6f92c2SWolfram Sang if (priv->adjust_hs400_calib_table)
439ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = true;
44026eb2607SMasaharu Hayakawa }
44126eb2607SMasaharu Hayakawa
renesas_sdhi_disable_scc(struct mmc_host * mmc)44280d0be81SWolfram Sang static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
44326eb2607SMasaharu Hayakawa {
44480d0be81SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc);
44580d0be81SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host);
44680d0be81SWolfram Sang
44726eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
44826eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
44926eb2607SMasaharu Hayakawa
45026eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
45126eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
45226eb2607SMasaharu Hayakawa sd_scc_read32(host, priv,
45326eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL));
45426eb2607SMasaharu Hayakawa
45526eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
45626eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
45726eb2607SMasaharu Hayakawa sd_scc_read32(host, priv,
45826eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL));
45926eb2607SMasaharu Hayakawa
46026eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
46126eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
46226eb2607SMasaharu Hayakawa }
46326eb2607SMasaharu Hayakawa
sd_scc_tmpport_read32(struct tmio_mmc_host * host,struct renesas_sdhi * priv,u32 addr)464ce6f92c2SWolfram Sang static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host,
465ce6f92c2SWolfram Sang struct renesas_sdhi *priv, u32 addr)
466ce6f92c2SWolfram Sang {
467ce6f92c2SWolfram Sang /* read mode */
468ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
469ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
470ce6f92c2SWolfram Sang (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
471ce6f92c2SWolfram Sang
472ce6f92c2SWolfram Sang /* access start and stop */
473ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
474ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
475ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
476ce6f92c2SWolfram Sang
477ce6f92c2SWolfram Sang return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7);
478ce6f92c2SWolfram Sang }
479ce6f92c2SWolfram Sang
sd_scc_tmpport_write32(struct tmio_mmc_host * host,struct renesas_sdhi * priv,u32 addr,u32 val)480ce6f92c2SWolfram Sang static void sd_scc_tmpport_write32(struct tmio_mmc_host *host,
481ce6f92c2SWolfram Sang struct renesas_sdhi *priv, u32 addr, u32 val)
482ce6f92c2SWolfram Sang {
483ce6f92c2SWolfram Sang /* write mode */
484ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
485ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
486ce6f92c2SWolfram Sang (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
487ce6f92c2SWolfram Sang
488ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val);
489ce6f92c2SWolfram Sang
490ce6f92c2SWolfram Sang /* access start and stop */
491ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
492ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
493ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
494ce6f92c2SWolfram Sang }
495ce6f92c2SWolfram Sang
renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host * host)496ce6f92c2SWolfram Sang static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host)
497ce6f92c2SWolfram Sang {
498ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host);
499ce6f92c2SWolfram Sang u32 calib_code;
500ce6f92c2SWolfram Sang
501ce6f92c2SWolfram Sang /* disable write protect */
502ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x00,
503ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
504ce6f92c2SWolfram Sang /* read calibration code and adjust */
505ce6f92c2SWolfram Sang calib_code = sd_scc_tmpport_read32(host, priv, 0x26);
506ce6f92c2SWolfram Sang calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
507ce6f92c2SWolfram Sang
508ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x22,
509ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE |
510ce6f92c2SWolfram Sang priv->adjust_hs400_calib_table[calib_code]);
511ce6f92c2SWolfram Sang
512ce6f92c2SWolfram Sang /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */
513ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3);
514ce6f92c2SWolfram Sang
515ce6f92c2SWolfram Sang /* adjustment done, clear flag */
516ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = false;
517ce6f92c2SWolfram Sang }
518ce6f92c2SWolfram Sang
renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host * host)519ce6f92c2SWolfram Sang static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host)
520ce6f92c2SWolfram Sang {
521ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host);
522ce6f92c2SWolfram Sang
523ce6f92c2SWolfram Sang /* disable write protect */
524ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x00,
525ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
526ce6f92c2SWolfram Sang /* disable manual calibration */
527ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x22, 0);
528ce6f92c2SWolfram Sang /* clear offset value of TMPPORT3 */
529ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0);
530ce6f92c2SWolfram Sang }
531ce6f92c2SWolfram Sang
renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host * host,struct renesas_sdhi * priv)53226eb2607SMasaharu Hayakawa static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
53326eb2607SMasaharu Hayakawa struct renesas_sdhi *priv)
53426eb2607SMasaharu Hayakawa {
53526eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
53626eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
53726eb2607SMasaharu Hayakawa
53826eb2607SMasaharu Hayakawa /* Reset HS400 mode */
5390e08a411SWolfram Sang sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 &
54026eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE));
541f0c8234cSTakeshi Saito
542f0c8234cSTakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
543f0c8234cSTakeshi Saito
54426eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
54526eb2607SMasaharu Hayakawa ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
54626eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
54726eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
54826eb2607SMasaharu Hayakawa
54948c917faSWolfram Sang if (sdhi_has_quirk(priv, hs400_calib_table) || sdhi_has_quirk(priv, hs400_bad_taps))
550ce6f92c2SWolfram Sang renesas_sdhi_adjust_hs400_mode_disable(host);
551ce6f92c2SWolfram Sang
55226eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
55326eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
55426eb2607SMasaharu Hayakawa }
55526eb2607SMasaharu Hayakawa
renesas_sdhi_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)556f22084b6SWolfram Sang static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
55726eb2607SMasaharu Hayakawa {
558f22084b6SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc);
559f22084b6SWolfram Sang
56026eb2607SMasaharu Hayakawa renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
561f22084b6SWolfram Sang return 0;
56226eb2607SMasaharu Hayakawa }
56326eb2607SMasaharu Hayakawa
renesas_sdhi_scc_reset(struct tmio_mmc_host * host,struct renesas_sdhi * priv)5640e587014SWolfram Sang static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv)
5655b0739d7SWolfram Sang {
566183edc06SWolfram Sang renesas_sdhi_disable_scc(host->mmc);
5675b0739d7SWolfram Sang renesas_sdhi_reset_hs400_mode(host, priv);
568ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = false;
5695b0739d7SWolfram Sang
5705b0739d7SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
5715b0739d7SWolfram Sang ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
5725b0739d7SWolfram Sang sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
57345bffc37SWolfram Sang }
5745b0739d7SWolfram Sang
5750e587014SWolfram Sang /* only populated for TMIO_MMC_MIN_RCAR2 */
renesas_sdhi_reset(struct tmio_mmc_host * host,bool preserve)5762e586f8aSWolfram Sang static void renesas_sdhi_reset(struct tmio_mmc_host *host, bool preserve)
5770e587014SWolfram Sang {
5780e587014SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host);
579b4d86f37SWolfram Sang int ret;
5800e587014SWolfram Sang u16 val;
5810e587014SWolfram Sang
5822e586f8aSWolfram Sang if (!preserve) {
583b4d86f37SWolfram Sang if (priv->rstc) {
584b4d86f37SWolfram Sang reset_control_reset(priv->rstc);
585b4d86f37SWolfram Sang /* Unknown why but without polling reset status, it will hang */
586b4d86f37SWolfram Sang read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100,
587b4d86f37SWolfram Sang false, priv->rstc);
588b81bede4SWolfram Sang /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */
589b81bede4SWolfram Sang sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
590b4d86f37SWolfram Sang priv->needs_adjust_hs400 = false;
591b4d86f37SWolfram Sang renesas_sdhi_set_clock(host, host->clk_cache);
592b4d86f37SWolfram Sang } else if (priv->scc_ctl) {
5930e587014SWolfram Sang renesas_sdhi_scc_reset(host, priv);
594b4d86f37SWolfram Sang }
5952e586f8aSWolfram Sang }
5960e587014SWolfram Sang
597b191deceSWolfram Sang if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) {
598b191deceSWolfram Sang val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
599b191deceSWolfram Sang val |= CARD_OPT_EXTOP;
600b191deceSWolfram Sang sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val);
601b191deceSWolfram Sang }
602b191deceSWolfram Sang }
603b191deceSWolfram Sang
renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host * host)604b191deceSWolfram Sang static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host)
605b191deceSWolfram Sang {
606b191deceSWolfram Sang u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
607b191deceSWolfram Sang
608b191deceSWolfram Sang num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT;
609b191deceSWolfram Sang return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num);
610b191deceSWolfram Sang
6115b0739d7SWolfram Sang }
6125b0739d7SWolfram Sang
613ec4fc1acSWolfram Sang #define SH_MOBILE_SDHI_MIN_TAP_ROW 3
614b5b6a5f4SSimon Horman
renesas_sdhi_select_tuning(struct tmio_mmc_host * host)615b5b6a5f4SSimon Horman static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
616b5b6a5f4SSimon Horman {
617b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host);
61892fa2a56SWolfram Sang unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
6195fb6bf51SWolfram Sang unsigned int taps_size = priv->tap_num * 2, min_tap_row;
6205fb6bf51SWolfram Sang unsigned long *bitmap;
621b5b6a5f4SSimon Horman
622b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
623b5b6a5f4SSimon Horman
624b5b6a5f4SSimon Horman /*
6255c99826bSNiklas Söderlund * When tuning CMD19 is issued twice for each tap, merge the
6265c99826bSNiklas Söderlund * result requiring the tap to be good in both runs before
6275c99826bSNiklas Söderlund * considering it for tuning selection.
6285c99826bSNiklas Söderlund */
62992fa2a56SWolfram Sang for (i = 0; i < taps_size; i++) {
630b2dd9a13SWolfram Sang int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
6315c99826bSNiklas Söderlund
632b2dd9a13SWolfram Sang if (!test_bit(i, priv->taps))
633b2dd9a13SWolfram Sang clear_bit(i + offset, priv->taps);
6345fb6bf51SWolfram Sang
6355fb6bf51SWolfram Sang if (!test_bit(i, priv->smpcmp))
6365fb6bf51SWolfram Sang clear_bit(i + offset, priv->smpcmp);
6375fb6bf51SWolfram Sang }
6385fb6bf51SWolfram Sang
6395fb6bf51SWolfram Sang /*
6405fb6bf51SWolfram Sang * If all TAP are OK, the sampling clock position is selected by
6415fb6bf51SWolfram Sang * identifying the change point of data.
6425fb6bf51SWolfram Sang */
6435fb6bf51SWolfram Sang if (bitmap_full(priv->taps, taps_size)) {
6445fb6bf51SWolfram Sang bitmap = priv->smpcmp;
6455fb6bf51SWolfram Sang min_tap_row = 1;
6465fb6bf51SWolfram Sang } else {
6475fb6bf51SWolfram Sang bitmap = priv->taps;
6485fb6bf51SWolfram Sang min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW;
6495c99826bSNiklas Söderlund }
6505c99826bSNiklas Söderlund
6515c99826bSNiklas Söderlund /*
652b5b6a5f4SSimon Horman * Find the longest consecutive run of successful probes. If that
653ec4fc1acSWolfram Sang * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the
654ec4fc1acSWolfram Sang * center index as the tap, otherwise bail out.
655b5b6a5f4SSimon Horman */
656ec288a2cSYury Norov for_each_set_bitrange(rs, re, bitmap, taps_size) {
65792fa2a56SWolfram Sang if (re - rs > tap_cnt) {
65892fa2a56SWolfram Sang tap_end = re;
65992fa2a56SWolfram Sang tap_start = rs;
66092fa2a56SWolfram Sang tap_cnt = tap_end - tap_start;
661b5b6a5f4SSimon Horman }
662b5b6a5f4SSimon Horman }
663b5b6a5f4SSimon Horman
6645fb6bf51SWolfram Sang if (tap_cnt >= min_tap_row)
665b2dd9a13SWolfram Sang priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
666b5b6a5f4SSimon Horman else
667b5b6a5f4SSimon Horman return -EIO;
668b5b6a5f4SSimon Horman
669b5b6a5f4SSimon Horman /* Set SCC */
670b2dd9a13SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
671b5b6a5f4SSimon Horman
672b5b6a5f4SSimon Horman /* Enable auto re-tuning */
673b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
674b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
675b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
676b5b6a5f4SSimon Horman
677b5b6a5f4SSimon Horman return 0;
678b5b6a5f4SSimon Horman }
679b5b6a5f4SSimon Horman
renesas_sdhi_execute_tuning(struct mmc_host * mmc,u32 opcode)680510bfe58SWolfram Sang static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode)
6810c482d82SWolfram Sang {
682510bfe58SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc);
6830c482d82SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host);
6845b0739d7SWolfram Sang int i, ret;
6850c482d82SWolfram Sang
686b2dd9a13SWolfram Sang priv->tap_num = renesas_sdhi_init_tuning(host);
687b2dd9a13SWolfram Sang if (!priv->tap_num)
6880c482d82SWolfram Sang return 0; /* Tuning is not supported */
6890c482d82SWolfram Sang
690b2dd9a13SWolfram Sang if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
6913a821a82SWolfram Sang dev_err(&host->pdev->dev,
6923a821a82SWolfram Sang "Too many taps, please update 'taps' in tmio_mmc_host!\n");
6933a821a82SWolfram Sang return -EINVAL;
6940c482d82SWolfram Sang }
6950c482d82SWolfram Sang
696b2dd9a13SWolfram Sang bitmap_zero(priv->taps, priv->tap_num * 2);
6975fb6bf51SWolfram Sang bitmap_zero(priv->smpcmp, priv->tap_num * 2);
6980c482d82SWolfram Sang
6990c482d82SWolfram Sang /* Issue CMD19 twice for each tap */
700b2dd9a13SWolfram Sang for (i = 0; i < 2 * priv->tap_num; i++) {
7017dba4028SWolfram Sang int cmd_error = 0;
7022c9017d0SWolfram Sang
7030c482d82SWolfram Sang /* Set sampling clock position */
704b2dd9a13SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
7050c482d82SWolfram Sang
7062c9017d0SWolfram Sang if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0)
707b2dd9a13SWolfram Sang set_bit(i, priv->taps);
7085fb6bf51SWolfram Sang
7095fb6bf51SWolfram Sang if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
7105fb6bf51SWolfram Sang set_bit(i, priv->smpcmp);
7112c9017d0SWolfram Sang
7122c9017d0SWolfram Sang if (cmd_error)
71321adc2e4SWolfram Sang mmc_send_abort_tuning(mmc, opcode);
7140c482d82SWolfram Sang }
7150c482d82SWolfram Sang
7165b0739d7SWolfram Sang ret = renesas_sdhi_select_tuning(host);
7175b0739d7SWolfram Sang if (ret < 0)
7180e587014SWolfram Sang renesas_sdhi_scc_reset(host, priv);
7195b0739d7SWolfram Sang return ret;
7200c482d82SWolfram Sang }
7210c482d82SWolfram Sang
renesas_sdhi_manual_correction(struct tmio_mmc_host * host,bool use_4tap)72211a21960STakeshi Saito static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
72311a21960STakeshi Saito {
72411a21960STakeshi Saito struct renesas_sdhi *priv = host_to_priv(host);
725a38c078fSTakeshi Saito unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set;
72611a21960STakeshi Saito u32 val;
72711a21960STakeshi Saito
72811a21960STakeshi Saito val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
72911a21960STakeshi Saito if (!val)
73011a21960STakeshi Saito return false;
73111a21960STakeshi Saito
73211a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
73311a21960STakeshi Saito
73411a21960STakeshi Saito /* Change TAP position according to correction status */
73548c917faSWolfram Sang if (sdhi_has_quirk(priv, manual_tap_correction) &&
73671cfc927STakeshi Saito host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
737a38c078fSTakeshi Saito u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
73871cfc927STakeshi Saito /*
73971cfc927STakeshi Saito * With HS400, the DAT signal is based on DS, not CLK.
74071cfc927STakeshi Saito * Therefore, use only CMD status.
74171cfc927STakeshi Saito */
74271cfc927STakeshi Saito u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
74371cfc927STakeshi Saito SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
744a38c078fSTakeshi Saito if (!smpcmp) {
74571cfc927STakeshi Saito return false; /* no error in CMD signal */
746a38c078fSTakeshi Saito } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) {
74771cfc927STakeshi Saito new_tap++;
748a38c078fSTakeshi Saito error_tap--;
749a38c078fSTakeshi Saito } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) {
75071cfc927STakeshi Saito new_tap--;
751a38c078fSTakeshi Saito error_tap++;
752a38c078fSTakeshi Saito } else {
75371cfc927STakeshi Saito return true; /* need retune */
754a38c078fSTakeshi Saito }
755a38c078fSTakeshi Saito
756a38c078fSTakeshi Saito /*
757a38c078fSTakeshi Saito * When new_tap is a bad tap, we cannot change. Then, we compare
758a38c078fSTakeshi Saito * with the HS200 tuning result. When smpcmp[error_tap] is OK,
759a38c078fSTakeshi Saito * we can at least retune.
760a38c078fSTakeshi Saito */
761a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap % priv->tap_num))
762a38c078fSTakeshi Saito return test_bit(error_tap % priv->tap_num, priv->smpcmp);
76371cfc927STakeshi Saito } else {
76411a21960STakeshi Saito if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
76571cfc927STakeshi Saito return true; /* need retune */
76611a21960STakeshi Saito else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
76771cfc927STakeshi Saito new_tap++;
76811a21960STakeshi Saito else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
76971cfc927STakeshi Saito new_tap--;
77011a21960STakeshi Saito else
77111a21960STakeshi Saito return false;
77271cfc927STakeshi Saito }
77311a21960STakeshi Saito
774b2dd9a13SWolfram Sang priv->tap_set = (new_tap % priv->tap_num);
77511a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
776b2dd9a13SWolfram Sang priv->tap_set / (use_4tap ? 2 : 1));
77711a21960STakeshi Saito
77811a21960STakeshi Saito return false;
77911a21960STakeshi Saito }
78011a21960STakeshi Saito
renesas_sdhi_auto_correction(struct tmio_mmc_host * host)78111a21960STakeshi Saito static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
78211a21960STakeshi Saito {
78311a21960STakeshi Saito struct renesas_sdhi *priv = host_to_priv(host);
78411a21960STakeshi Saito
78511a21960STakeshi Saito /* Check SCC error */
78611a21960STakeshi Saito if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
78711a21960STakeshi Saito SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
78811a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
78911a21960STakeshi Saito return true;
79011a21960STakeshi Saito }
79111a21960STakeshi Saito
79211a21960STakeshi Saito return false;
79311a21960STakeshi Saito }
79411a21960STakeshi Saito
renesas_sdhi_check_scc_error(struct tmio_mmc_host * host,struct mmc_request * mrq)795ed2fab9aSYoshihiro Shimoda static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host,
796ed2fab9aSYoshihiro Shimoda struct mmc_request *mrq)
797b5b6a5f4SSimon Horman {
798b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host);
79948c917faSWolfram Sang bool use_4tap = sdhi_has_quirk(priv, hs400_4taps);
800ed2fab9aSYoshihiro Shimoda bool ret = false;
80175f349a1SMasaharu Hayakawa
80275f349a1SMasaharu Hayakawa /*
80375f349a1SMasaharu Hayakawa * Skip checking SCC errors when running on 4 taps in HS400 mode as
80475f349a1SMasaharu Hayakawa * any retuning would still result in the same 4 taps being used.
80575f349a1SMasaharu Hayakawa */
80675f349a1SMasaharu Hayakawa if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
80775f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
80875f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
80975f349a1SMasaharu Hayakawa return false;
81075f349a1SMasaharu Hayakawa
811fbb31330SWolfram Sang if (mmc_doing_tune(host->mmc))
81275f349a1SMasaharu Hayakawa return false;
813b5b6a5f4SSimon Horman
814ed2fab9aSYoshihiro Shimoda if (((mrq->cmd->error == -ETIMEDOUT) ||
815ed2fab9aSYoshihiro Shimoda (mrq->data && mrq->data->error == -ETIMEDOUT)) &&
816ed2fab9aSYoshihiro Shimoda ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
817ed2fab9aSYoshihiro Shimoda (host->ops.get_cd && host->ops.get_cd(host->mmc))))
818ed2fab9aSYoshihiro Shimoda ret |= true;
819ed2fab9aSYoshihiro Shimoda
820b5b6a5f4SSimon Horman if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
82111a21960STakeshi Saito SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
822ed2fab9aSYoshihiro Shimoda ret |= renesas_sdhi_auto_correction(host);
823ed2fab9aSYoshihiro Shimoda else
824ed2fab9aSYoshihiro Shimoda ret |= renesas_sdhi_manual_correction(host, use_4tap);
825b5b6a5f4SSimon Horman
826ed2fab9aSYoshihiro Shimoda return ret;
827b5b6a5f4SSimon Horman }
828b5b6a5f4SSimon Horman
renesas_sdhi_wait_idle(struct tmio_mmc_host * host,u32 bit)8294dc48a95SWolfram Sang static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
830b5b6a5f4SSimon Horman {
831b5b6a5f4SSimon Horman int timeout = 1000;
8324dc48a95SWolfram Sang /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
8334dc48a95SWolfram Sang u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
834b5b6a5f4SSimon Horman
8354dc48a95SWolfram Sang while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
8364dc48a95SWolfram Sang & bit) == wait_state)
837b5b6a5f4SSimon Horman udelay(1);
838b5b6a5f4SSimon Horman
839b5b6a5f4SSimon Horman if (!timeout) {
840b5b6a5f4SSimon Horman dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
841b5b6a5f4SSimon Horman return -EBUSY;
842b5b6a5f4SSimon Horman }
843b5b6a5f4SSimon Horman
844b5b6a5f4SSimon Horman return 0;
845b5b6a5f4SSimon Horman }
846b5b6a5f4SSimon Horman
renesas_sdhi_write16_hook(struct tmio_mmc_host * host,int addr)847b5b6a5f4SSimon Horman static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
848b5b6a5f4SSimon Horman {
8494dc48a95SWolfram Sang u32 bit = TMIO_STAT_SCLKDIVEN;
8504dc48a95SWolfram Sang
8512fe35968SSimon Horman switch (addr) {
852b5b6a5f4SSimon Horman case CTL_SD_CMD:
853b5b6a5f4SSimon Horman case CTL_STOP_INTERNAL_ACTION:
854b5b6a5f4SSimon Horman case CTL_XFER_BLK_COUNT:
855b5b6a5f4SSimon Horman case CTL_SD_XFER_LEN:
856b5b6a5f4SSimon Horman case CTL_SD_MEM_CARD_OPT:
857b5b6a5f4SSimon Horman case CTL_TRANSACTION_CTL:
858b5b6a5f4SSimon Horman case CTL_DMA_ENABLE:
8594533c3ebSWolfram Sang case CTL_HOST_MODE:
8605124b592SWolfram Sang if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
8614dc48a95SWolfram Sang bit = TMIO_STAT_CMD_BUSY;
862df561f66SGustavo A. R. Silva fallthrough;
8634dc48a95SWolfram Sang case CTL_SD_CARD_CLK_CTL:
8644dc48a95SWolfram Sang return renesas_sdhi_wait_idle(host, bit);
865b5b6a5f4SSimon Horman }
866b5b6a5f4SSimon Horman
867b5b6a5f4SSimon Horman return 0;
868b5b6a5f4SSimon Horman }
869b5b6a5f4SSimon Horman
renesas_sdhi_multi_io_quirk(struct mmc_card * card,unsigned int direction,int blk_size)870b5b6a5f4SSimon Horman static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
871b5b6a5f4SSimon Horman unsigned int direction, int blk_size)
872b5b6a5f4SSimon Horman {
873b5b6a5f4SSimon Horman /*
874b5b6a5f4SSimon Horman * In Renesas controllers, when performing a
875b5b6a5f4SSimon Horman * multiple block read of one or two blocks,
876b5b6a5f4SSimon Horman * depending on the timing with which the
877b5b6a5f4SSimon Horman * response register is read, the response
878b5b6a5f4SSimon Horman * value may not be read properly.
879b5b6a5f4SSimon Horman * Use single block read for this HW bug
880b5b6a5f4SSimon Horman */
881b5b6a5f4SSimon Horman if ((direction == MMC_DATA_READ) &&
882b5b6a5f4SSimon Horman blk_size == 2)
883b5b6a5f4SSimon Horman return 1;
884b5b6a5f4SSimon Horman
885b5b6a5f4SSimon Horman return blk_size;
886b5b6a5f4SSimon Horman }
887b5b6a5f4SSimon Horman
renesas_sdhi_fixup_request(struct tmio_mmc_host * host,struct mmc_request * mrq)888ce6f92c2SWolfram Sang static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq)
889ce6f92c2SWolfram Sang {
890ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host);
891ce6f92c2SWolfram Sang
892ce6f92c2SWolfram Sang if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS)
893ce6f92c2SWolfram Sang renesas_sdhi_adjust_hs400_mode_enable(host);
894ce6f92c2SWolfram Sang }
renesas_sdhi_enable_dma(struct tmio_mmc_host * host,bool enable)895b5b6a5f4SSimon Horman static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
896b5b6a5f4SSimon Horman {
89741279f01SWolfram Sang /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
89841279f01SWolfram Sang int width = (host->bus_shift == 2) ? 64 : 32;
899b5b6a5f4SSimon Horman
90041279f01SWolfram Sang sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
90141279f01SWolfram Sang renesas_sdhi_sdbuf_width(host, enable ? width : 16);
902b5b6a5f4SSimon Horman }
903b5b6a5f4SSimon Horman
renesas_sdhi_probe(struct platform_device * pdev,const struct tmio_mmc_dma_ops * dma_ops,const struct renesas_sdhi_of_data * of_data,const struct renesas_sdhi_quirks * quirks)9049d08428aSSimon Horman int renesas_sdhi_probe(struct platform_device *pdev,
90571b7597cSYoshihiro Shimoda const struct tmio_mmc_dma_ops *dma_ops,
90671b7597cSYoshihiro Shimoda const struct renesas_sdhi_of_data *of_data,
90771b7597cSYoshihiro Shimoda const struct renesas_sdhi_quirks *quirks)
908b5b6a5f4SSimon Horman {
909b5b6a5f4SSimon Horman struct tmio_mmc_data *mmd = pdev->dev.platform_data;
9102fe35968SSimon Horman struct tmio_mmc_data *mmc_data;
9117f3ea248SWolfram Sang struct renesas_sdhi_dma *dma_priv;
912b5b6a5f4SSimon Horman struct tmio_mmc_host *host;
9132fe35968SSimon Horman struct renesas_sdhi *priv;
914e8307ec5SGeert Uytterhoeven int num_irqs, irq, ret, i;
915b5b6a5f4SSimon Horman struct resource *res;
916c9a9497cSWolfram Sang u16 ver;
9172fe35968SSimon Horman
918b5b6a5f4SSimon Horman res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
919b5b6a5f4SSimon Horman if (!res)
920b5b6a5f4SSimon Horman return -EINVAL;
921b5b6a5f4SSimon Horman
9222fe35968SSimon Horman priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
9232fe35968SSimon Horman GFP_KERNEL);
924b5b6a5f4SSimon Horman if (!priv)
925b5b6a5f4SSimon Horman return -ENOMEM;
926b5b6a5f4SSimon Horman
9277af08206SWolfram Sang priv->quirks = quirks;
928b5b6a5f4SSimon Horman mmc_data = &priv->mmc_data;
929b5b6a5f4SSimon Horman dma_priv = &priv->dma_priv;
930b5b6a5f4SSimon Horman
931b5b6a5f4SSimon Horman priv->clk = devm_clk_get(&pdev->dev, NULL);
932079e83b9SWolfram Sang if (IS_ERR(priv->clk))
933079e83b9SWolfram Sang return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock");
934b5b6a5f4SSimon Horman
935e5f7e81eSWolfram Sang priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh");
936e5f7e81eSWolfram Sang if (IS_ERR(priv->clkh))
937e5f7e81eSWolfram Sang return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkh), "cannot get clkh");
938b5b6a5f4SSimon Horman
939b5b6a5f4SSimon Horman /*
940b5b6a5f4SSimon Horman * Some controllers provide a 2nd clock just to run the internal card
941b5b6a5f4SSimon Horman * detection logic. Unfortunately, the existing driver architecture does
942b5b6a5f4SSimon Horman * not support a separation of clocks for runtime PM usage. When
943b5b6a5f4SSimon Horman * native hotplug is used, the tmio driver assumes that the core
944b5b6a5f4SSimon Horman * must continue to run for card detect to stay active, so we cannot
945b5b6a5f4SSimon Horman * disable it.
946b5b6a5f4SSimon Horman * Additionally, it is prohibited to supply a clock to the core but not
947b5b6a5f4SSimon Horman * to the card detect circuit. That leaves us with if separate clocks
948b5b6a5f4SSimon Horman * are presented, we must treat them both as virtually 1 clock.
949b5b6a5f4SSimon Horman */
950366df82fSGeert Uytterhoeven priv->clk_cd = devm_clk_get_optional(&pdev->dev, "cd");
951b5b6a5f4SSimon Horman if (IS_ERR(priv->clk_cd))
952366df82fSGeert Uytterhoeven return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cd), "cannot get cd clock");
953b5b6a5f4SSimon Horman
9540dac1e49SLad Prabhakar priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
9550dac1e49SLad Prabhakar if (IS_ERR(priv->rstc))
9560dac1e49SLad Prabhakar return PTR_ERR(priv->rstc);
9570dac1e49SLad Prabhakar
958b5b6a5f4SSimon Horman priv->pinctrl = devm_pinctrl_get(&pdev->dev);
959b5b6a5f4SSimon Horman if (!IS_ERR(priv->pinctrl)) {
960b5b6a5f4SSimon Horman priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
961b5b6a5f4SSimon Horman PINCTRL_STATE_DEFAULT);
962b5b6a5f4SSimon Horman priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
963b5b6a5f4SSimon Horman "state_uhs");
964b5b6a5f4SSimon Horman }
965b5b6a5f4SSimon Horman
966b21fc294SMasahiro Yamada host = tmio_mmc_host_alloc(pdev, mmc_data);
9678d09a133SMasahiro Yamada if (IS_ERR(host))
9688d09a133SMasahiro Yamada return PTR_ERR(host);
969b5b6a5f4SSimon Horman
970b5b6a5f4SSimon Horman if (of_data) {
971b5b6a5f4SSimon Horman mmc_data->flags |= of_data->tmio_flags;
972b5b6a5f4SSimon Horman mmc_data->ocr_mask = of_data->tmio_ocr_mask;
973b5b6a5f4SSimon Horman mmc_data->capabilities |= of_data->capabilities;
974b5b6a5f4SSimon Horman mmc_data->capabilities2 |= of_data->capabilities2;
975b5b6a5f4SSimon Horman mmc_data->dma_rx_offset = of_data->dma_rx_offset;
976603aa14dSYoshihiro Shimoda mmc_data->max_blk_count = of_data->max_blk_count;
977603aa14dSYoshihiro Shimoda mmc_data->max_segs = of_data->max_segs;
978b5b6a5f4SSimon Horman dma_priv->dma_buswidth = of_data->dma_buswidth;
979b5b6a5f4SSimon Horman host->bus_shift = of_data->bus_shift;
980bb6d3fa9SWolfram Sang /* Fallback for old DTs */
981e5f7e81eSWolfram Sang if (!priv->clkh && of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK)
982bb6d3fa9SWolfram Sang priv->clkh = clk_get_parent(clk_get_parent(priv->clk));
983bb6d3fa9SWolfram Sang
984b5b6a5f4SSimon Horman }
985b5b6a5f4SSimon Horman
986b5b6a5f4SSimon Horman host->write16_hook = renesas_sdhi_write16_hook;
987b5b6a5f4SSimon Horman host->clk_enable = renesas_sdhi_clk_enable;
988b5b6a5f4SSimon Horman host->clk_disable = renesas_sdhi_clk_disable;
9890196c8dbSMasahiro Yamada host->set_clock = renesas_sdhi_set_clock;
990b5b6a5f4SSimon Horman host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
991bc45719cSMasahiro Yamada host->dma_ops = dma_ops;
992b5b6a5f4SSimon Horman
99348c917faSWolfram Sang if (sdhi_has_quirk(priv, hs400_disabled))
9940f4e2054SNiklas Söderlund host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
9950f4e2054SNiklas Söderlund
996ef5332c1SWolfram Sang /* For some SoC, we disable internal WP. GPIO may override this */
997ef5332c1SWolfram Sang if (mmc_can_gpio_ro(host->mmc))
998ef5332c1SWolfram Sang mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
999ef5332c1SWolfram Sang
1000b5b6a5f4SSimon Horman /* SDR speeds are only available on Gen2+ */
1001b5b6a5f4SSimon Horman if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
1002b5b6a5f4SSimon Horman /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
10032aaa3c51SMasahiro Yamada host->ops.card_busy = renesas_sdhi_card_busy;
10042aaa3c51SMasahiro Yamada host->ops.start_signal_voltage_switch =
1005b5b6a5f4SSimon Horman renesas_sdhi_start_signal_voltage_switch;
10061970701fSWolfram Sang host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
10079f12cac1SWolfram Sang host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2;
10086e7d4de1SWolfram Sang host->reset = renesas_sdhi_reset;
100974f45de3SWolfram Sang } else {
101074f45de3SWolfram Sang host->sdcard_irq_mask_all = TMIO_MASK_ALL;
1011d30ae056STakeshi Saito }
1012b5b6a5f4SSimon Horman
1013b5b6a5f4SSimon Horman /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
1014b5b6a5f4SSimon Horman if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
1015b5b6a5f4SSimon Horman host->bus_shift = 1;
1016b5b6a5f4SSimon Horman
1017b5b6a5f4SSimon Horman if (mmd)
1018b5b6a5f4SSimon Horman *mmc_data = *mmd;
1019b5b6a5f4SSimon Horman
1020b5b6a5f4SSimon Horman dma_priv->filter = shdma_chan_filter;
1021b5b6a5f4SSimon Horman dma_priv->enable = renesas_sdhi_enable_dma;
1022b5b6a5f4SSimon Horman
1023b5b6a5f4SSimon Horman mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1024b5b6a5f4SSimon Horman
1025b5b6a5f4SSimon Horman /*
1026b5b6a5f4SSimon Horman * All SDHI blocks support 2-byte and larger block sizes in 4-bit
1027b5b6a5f4SSimon Horman * bus width mode.
1028b5b6a5f4SSimon Horman */
1029b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
1030b5b6a5f4SSimon Horman
1031b5b6a5f4SSimon Horman /*
1032b5b6a5f4SSimon Horman * All SDHI blocks support SDIO IRQ signalling.
1033b5b6a5f4SSimon Horman */
1034b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
1035b5b6a5f4SSimon Horman
10362fe35968SSimon Horman /* All SDHI have CMD12 control bit */
1037b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
1038b5b6a5f4SSimon Horman
1039b5b6a5f4SSimon Horman /* All SDHI have SDIO status bits which must be 1 */
1040b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
1041b5b6a5f4SSimon Horman
104230ae3e13SWolfram Sang /* All SDHI support HW busy detection */
104330ae3e13SWolfram Sang mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT;
104430ae3e13SWolfram Sang
104563fd8ef3SUlf Hansson dev_pm_domain_start(&pdev->dev);
104663fd8ef3SUlf Hansson
1047b21fc294SMasahiro Yamada ret = renesas_sdhi_clk_enable(host);
1048b21fc294SMasahiro Yamada if (ret)
1049b5b6a5f4SSimon Horman goto efree;
1050b5b6a5f4SSimon Horman
1051c9a9497cSWolfram Sang ver = sd_ctrl_read16(host, CTL_VERSION);
1052c9a9497cSWolfram Sang /* GEN2_SDR104 is first known SDHI to use 32bit block count */
1053c9a9497cSWolfram Sang if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
1054c9a9497cSWolfram Sang mmc_data->max_blk_count = U16_MAX;
1055c9a9497cSWolfram Sang
10565124b592SWolfram Sang /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
1057c9a9497cSWolfram Sang if (ver == SDHI_VER_GEN2_SDR50)
10585124b592SWolfram Sang mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
10595124b592SWolfram Sang
106048c917faSWolfram Sang if (ver == SDHI_VER_GEN3_SDMMC && sdhi_has_quirk(priv, hs400_calib_table)) {
1061ce6f92c2SWolfram Sang host->fixup_request = renesas_sdhi_fixup_request;
1062ce6f92c2SWolfram Sang priv->adjust_hs400_calib_table = *(
1063ce6f92c2SWolfram Sang res->start == SDHI_GEN3_MMC0_ADDR ?
1064ce6f92c2SWolfram Sang quirks->hs400_calib_table :
1065ce6f92c2SWolfram Sang quirks->hs400_calib_table + 1);
1066ce6f92c2SWolfram Sang }
1067ce6f92c2SWolfram Sang
1068b191deceSWolfram Sang /* these have an EXTOP bit */
1069b191deceSWolfram Sang if (ver >= SDHI_VER_GEN3_SD)
1070b191deceSWolfram Sang host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles;
1071b191deceSWolfram Sang
10723d4f9898SWolfram Sang /* Check for SCC so we can reset it if needed */
10733d4f9898SWolfram Sang if (of_data && of_data->scc_offset && ver >= SDHI_VER_GEN2_SDR104)
10743d4f9898SWolfram Sang priv->scc_ctl = host->ctl + of_data->scc_offset;
10753d4f9898SWolfram Sang
1076b5b6a5f4SSimon Horman /* Enable tuning iff we have an SCC and a supported mode */
10773d4f9898SWolfram Sang if (priv->scc_ctl && (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
1078afc9b96bSWolfram Sang host->mmc->caps2 & MMC_CAP2_HSX00_1_8V)) {
1079b5b6a5f4SSimon Horman const struct renesas_sdhi_scc *taps = of_data->taps;
108048c917faSWolfram Sang bool use_4tap = sdhi_has_quirk(priv, hs400_4taps);
1081b5b6a5f4SSimon Horman bool hit = false;
1082b5b6a5f4SSimon Horman
1083b5b6a5f4SSimon Horman for (i = 0; i < of_data->taps_num; i++) {
1084b5b6a5f4SSimon Horman if (taps[i].clk_rate == 0 ||
1085b5b6a5f4SSimon Horman taps[i].clk_rate == host->mmc->f_max) {
1086852d258fSMasahiro Yamada priv->scc_tappos = taps->tap;
1087c1a49782SWolfram Sang priv->scc_tappos_hs400 = use_4tap ?
1088c1a49782SWolfram Sang taps->tap_hs400_4tap :
1089c1a49782SWolfram Sang taps->tap;
1090b5b6a5f4SSimon Horman hit = true;
1091b5b6a5f4SSimon Horman break;
1092b5b6a5f4SSimon Horman }
1093b5b6a5f4SSimon Horman }
1094b5b6a5f4SSimon Horman
1095b5b6a5f4SSimon Horman if (!hit)
1096e5088f20SWolfram Sang dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
1097b5b6a5f4SSimon Horman
109864982b9fSWolfram Sang host->check_retune = renesas_sdhi_check_scc_error;
1099510bfe58SWolfram Sang host->ops.execute_tuning = renesas_sdhi_execute_tuning;
1100f22084b6SWolfram Sang host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
1101f22084b6SWolfram Sang host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
1102f22084b6SWolfram Sang host->ops.hs400_complete = renesas_sdhi_hs400_complete;
1103b5b6a5f4SSimon Horman }
1104b5b6a5f4SSimon Horman
110574f45de3SWolfram Sang sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask_all);
1106b161d87dSWolfram Sang
1107e8307ec5SGeert Uytterhoeven num_irqs = platform_irq_count(pdev);
1108e8307ec5SGeert Uytterhoeven if (num_irqs < 0) {
1109e8307ec5SGeert Uytterhoeven ret = num_irqs;
1110b5b6a5f4SSimon Horman goto eirq;
1111b5b6a5f4SSimon Horman }
1112b5b6a5f4SSimon Horman
1113b5b6a5f4SSimon Horman /* There must be at least one IRQ source */
1114e8307ec5SGeert Uytterhoeven if (!num_irqs) {
1115e8307ec5SGeert Uytterhoeven ret = -ENXIO;
1116e8307ec5SGeert Uytterhoeven goto eirq;
1117e8307ec5SGeert Uytterhoeven }
1118e8307ec5SGeert Uytterhoeven
1119e8307ec5SGeert Uytterhoeven for (i = 0; i < num_irqs; i++) {
1120e8307ec5SGeert Uytterhoeven irq = platform_get_irq(pdev, i);
1121e8307ec5SGeert Uytterhoeven if (irq < 0) {
1122b5b6a5f4SSimon Horman ret = irq;
1123b5b6a5f4SSimon Horman goto eirq;
1124b5b6a5f4SSimon Horman }
1125b5b6a5f4SSimon Horman
1126e8307ec5SGeert Uytterhoeven ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
1127e8307ec5SGeert Uytterhoeven dev_name(&pdev->dev), host);
1128e8307ec5SGeert Uytterhoeven if (ret)
1129e8307ec5SGeert Uytterhoeven goto eirq;
1130e8307ec5SGeert Uytterhoeven }
1131e8307ec5SGeert Uytterhoeven
113274f45de3SWolfram Sang ret = tmio_mmc_host_probe(host);
113374f45de3SWolfram Sang if (ret < 0)
113474f45de3SWolfram Sang goto edisclk;
113574f45de3SWolfram Sang
1136bcf89cb8SWolfram Sang dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
1137bcf89cb8SWolfram Sang mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
1138b5b6a5f4SSimon Horman
1139b5b6a5f4SSimon Horman return ret;
1140b5b6a5f4SSimon Horman
1141b5b6a5f4SSimon Horman eirq:
1142b5b6a5f4SSimon Horman tmio_mmc_host_remove(host);
1143b21fc294SMasahiro Yamada edisclk:
1144b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host);
1145b5b6a5f4SSimon Horman efree:
1146b5b6a5f4SSimon Horman tmio_mmc_host_free(host);
11474ce62817SMasahiro Yamada
1148b5b6a5f4SSimon Horman return ret;
1149b5b6a5f4SSimon Horman }
11509d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
1151b5b6a5f4SSimon Horman
renesas_sdhi_remove(struct platform_device * pdev)1152*80c602b1SYangtao Li void renesas_sdhi_remove(struct platform_device *pdev)
1153b5b6a5f4SSimon Horman {
1154a3b05373SMasahiro Yamada struct tmio_mmc_host *host = platform_get_drvdata(pdev);
1155b5b6a5f4SSimon Horman
1156b5b6a5f4SSimon Horman tmio_mmc_host_remove(host);
1157b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host);
1158e8973201SYoshihiro Shimoda tmio_mmc_host_free(host);
1159b5b6a5f4SSimon Horman }
11609d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
1161967a6a07SMasaharu Hayakawa
1162967a6a07SMasaharu Hayakawa MODULE_LICENSE("GPL v2");
1163