183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2e94cad93SMarek Vasut /*
3e94cad93SMarek Vasut * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
4e94cad93SMarek Vasut */
5e94cad93SMarek Vasut
6e94cad93SMarek Vasut #include <common.h>
7e94cad93SMarek Vasut #include <clk.h>
8e94cad93SMarek Vasut #include <fdtdec.h>
9e94cad93SMarek Vasut #include <mmc.h>
10e94cad93SMarek Vasut #include <dm.h>
11e94cad93SMarek Vasut #include <linux/compat.h>
12e94cad93SMarek Vasut #include <linux/dma-direction.h>
13e94cad93SMarek Vasut #include <linux/io.h>
14e94cad93SMarek Vasut #include <linux/sizes.h>
15e94cad93SMarek Vasut #include <power/regulator.h>
16e94cad93SMarek Vasut #include <asm/unaligned.h>
17e94cad93SMarek Vasut
18cb0b6b03SMarek Vasut #include "tmio-common.h"
19e94cad93SMarek Vasut
2050aa1d99SMarek Vasut #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
2150aa1d99SMarek Vasut CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2250aa1d99SMarek Vasut CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
23f63968baSMarek Vasut
24f63968baSMarek Vasut /* SCC registers */
25f63968baSMarek Vasut #define RENESAS_SDHI_SCC_DTCNTL 0x800
26f63968baSMarek Vasut #define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
27f63968baSMarek Vasut #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
28f63968baSMarek Vasut #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
29f63968baSMarek Vasut #define RENESAS_SDHI_SCC_TAPSET 0x804
30f63968baSMarek Vasut #define RENESAS_SDHI_SCC_DT2FF 0x808
31f63968baSMarek Vasut #define RENESAS_SDHI_SCC_CKSEL 0x80c
32f63968baSMarek Vasut #define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
33f63968baSMarek Vasut #define RENESAS_SDHI_SCC_RVSCNTL 0x810
34f63968baSMarek Vasut #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
35f63968baSMarek Vasut #define RENESAS_SDHI_SCC_RVSREQ 0x814
36f63968baSMarek Vasut #define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
37f63968baSMarek Vasut #define RENESAS_SDHI_SCC_SMPCMP 0x818
38f63968baSMarek Vasut #define RENESAS_SDHI_SCC_TMPPORT2 0x81c
39dc1488f1SMarek Vasut #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
40dc1488f1SMarek Vasut #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
41f63968baSMarek Vasut
42f63968baSMarek Vasut #define RENESAS_SDHI_MAX_TAP 3
43f63968baSMarek Vasut
renesas_sdhi_init_tuning(struct tmio_sd_priv * priv)44cb0b6b03SMarek Vasut static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
45f63968baSMarek Vasut {
46f63968baSMarek Vasut u32 reg;
47f63968baSMarek Vasut
48f63968baSMarek Vasut /* Initialize SCC */
49cb0b6b03SMarek Vasut tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
50f63968baSMarek Vasut
51cb0b6b03SMarek Vasut reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
52cb0b6b03SMarek Vasut reg &= ~TMIO_SD_CLKCTL_SCLKEN;
53cb0b6b03SMarek Vasut tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
54f63968baSMarek Vasut
55f63968baSMarek Vasut /* Set sampling clock selection range */
56a376dde1SMarek Vasut tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
57a376dde1SMarek Vasut RENESAS_SDHI_SCC_DTCNTL_TAPEN,
58f63968baSMarek Vasut RENESAS_SDHI_SCC_DTCNTL);
59f63968baSMarek Vasut
60cb0b6b03SMarek Vasut reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
61f63968baSMarek Vasut reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
62cb0b6b03SMarek Vasut tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
63f63968baSMarek Vasut
64cb0b6b03SMarek Vasut reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
65f63968baSMarek Vasut reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
66cb0b6b03SMarek Vasut tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
67f63968baSMarek Vasut
68cb0b6b03SMarek Vasut tmio_sd_writel(priv, 0x300 /* scc_tappos */,
69f63968baSMarek Vasut RENESAS_SDHI_SCC_DT2FF);
70f63968baSMarek Vasut
71cb0b6b03SMarek Vasut reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
72cb0b6b03SMarek Vasut reg |= TMIO_SD_CLKCTL_SCLKEN;
73cb0b6b03SMarek Vasut tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
74f63968baSMarek Vasut
75f63968baSMarek Vasut /* Read TAPNUM */
76cb0b6b03SMarek Vasut return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
77f63968baSMarek Vasut RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
78f63968baSMarek Vasut RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
79f63968baSMarek Vasut }
80f63968baSMarek Vasut
renesas_sdhi_reset_tuning(struct tmio_sd_priv * priv)81cb0b6b03SMarek Vasut static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
82f63968baSMarek Vasut {
83f63968baSMarek Vasut u32 reg;
84f63968baSMarek Vasut
85f63968baSMarek Vasut /* Reset SCC */
86cb0b6b03SMarek Vasut reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
87cb0b6b03SMarek Vasut reg &= ~TMIO_SD_CLKCTL_SCLKEN;
88cb0b6b03SMarek Vasut tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
89f63968baSMarek Vasut
90cb0b6b03SMarek Vasut reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
91f63968baSMarek Vasut reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
92cb0b6b03SMarek Vasut tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
93f63968baSMarek Vasut
94dc1488f1SMarek Vasut reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
95dc1488f1SMarek Vasut reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
96dc1488f1SMarek Vasut RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
97dc1488f1SMarek Vasut tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
98dc1488f1SMarek Vasut
99cb0b6b03SMarek Vasut reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
100cb0b6b03SMarek Vasut reg |= TMIO_SD_CLKCTL_SCLKEN;
101cb0b6b03SMarek Vasut tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
102f63968baSMarek Vasut
103cb0b6b03SMarek Vasut reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
104f63968baSMarek Vasut reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
105cb0b6b03SMarek Vasut tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
106f63968baSMarek Vasut
107cb0b6b03SMarek Vasut reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
108f63968baSMarek Vasut reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
109cb0b6b03SMarek Vasut tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
110f63968baSMarek Vasut }
111f63968baSMarek Vasut
renesas_sdhi_hs400(struct udevice * dev)11250aa1d99SMarek Vasut static int renesas_sdhi_hs400(struct udevice *dev)
11350aa1d99SMarek Vasut {
11450aa1d99SMarek Vasut struct tmio_sd_priv *priv = dev_get_priv(dev);
11550aa1d99SMarek Vasut struct mmc *mmc = mmc_get_mmc_dev(dev);
11650aa1d99SMarek Vasut bool hs400 = (mmc->selected_mode == MMC_HS_400);
11750aa1d99SMarek Vasut int ret, taps = hs400 ? priv->nrtaps : 8;
11850aa1d99SMarek Vasut u32 reg;
11950aa1d99SMarek Vasut
12050aa1d99SMarek Vasut if (taps == 4) /* HS400 on 4tap SoC needs different clock */
12150aa1d99SMarek Vasut ret = clk_set_rate(&priv->clk, 400000000);
12250aa1d99SMarek Vasut else
12350aa1d99SMarek Vasut ret = clk_set_rate(&priv->clk, 200000000);
12450aa1d99SMarek Vasut if (ret < 0)
12550aa1d99SMarek Vasut return ret;
12650aa1d99SMarek Vasut
12750aa1d99SMarek Vasut tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
12850aa1d99SMarek Vasut
12950aa1d99SMarek Vasut reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
13050aa1d99SMarek Vasut if (hs400) {
13150aa1d99SMarek Vasut reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
13250aa1d99SMarek Vasut RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
13350aa1d99SMarek Vasut } else {
13450aa1d99SMarek Vasut reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
13550aa1d99SMarek Vasut RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
13650aa1d99SMarek Vasut }
13750aa1d99SMarek Vasut
13850aa1d99SMarek Vasut tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
13950aa1d99SMarek Vasut
140*ba41c45eSMarek Vasut tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
14150aa1d99SMarek Vasut RENESAS_SDHI_SCC_DTCNTL_TAPEN,
14250aa1d99SMarek Vasut RENESAS_SDHI_SCC_DTCNTL);
14350aa1d99SMarek Vasut
14450aa1d99SMarek Vasut if (taps == 4) {
14550aa1d99SMarek Vasut tmio_sd_writel(priv, priv->tap_set >> 1,
14650aa1d99SMarek Vasut RENESAS_SDHI_SCC_TAPSET);
14750aa1d99SMarek Vasut } else {
14850aa1d99SMarek Vasut tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
14950aa1d99SMarek Vasut }
15050aa1d99SMarek Vasut
151261445dfSMarek Vasut tmio_sd_writel(priv, hs400 ? 0x704 : 0x300,
152261445dfSMarek Vasut RENESAS_SDHI_SCC_DT2FF);
153261445dfSMarek Vasut
15450aa1d99SMarek Vasut reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
15550aa1d99SMarek Vasut reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
15650aa1d99SMarek Vasut tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
15750aa1d99SMarek Vasut
15850aa1d99SMarek Vasut reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
15950aa1d99SMarek Vasut reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
16050aa1d99SMarek Vasut tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
16150aa1d99SMarek Vasut
16250aa1d99SMarek Vasut return 0;
16350aa1d99SMarek Vasut }
16450aa1d99SMarek Vasut
renesas_sdhi_prepare_tuning(struct tmio_sd_priv * priv,unsigned long tap)165cb0b6b03SMarek Vasut static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
166f63968baSMarek Vasut unsigned long tap)
167f63968baSMarek Vasut {
168f63968baSMarek Vasut /* Set sampling clock position */
169cb0b6b03SMarek Vasut tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
170f63968baSMarek Vasut }
171f63968baSMarek Vasut
renesas_sdhi_compare_scc_data(struct tmio_sd_priv * priv)172cb0b6b03SMarek Vasut static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
173f63968baSMarek Vasut {
174f63968baSMarek Vasut /* Get comparison of sampling data */
175cb0b6b03SMarek Vasut return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
176f63968baSMarek Vasut }
177f63968baSMarek Vasut
renesas_sdhi_select_tuning(struct tmio_sd_priv * priv,unsigned int tap_num,unsigned int taps,unsigned int smpcmp)178cb0b6b03SMarek Vasut static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
179f63968baSMarek Vasut unsigned int tap_num, unsigned int taps,
180f63968baSMarek Vasut unsigned int smpcmp)
181f63968baSMarek Vasut {
182f63968baSMarek Vasut unsigned long tap_cnt; /* counter of tuning success */
183f63968baSMarek Vasut unsigned long tap_start;/* start position of tuning success */
184f63968baSMarek Vasut unsigned long tap_end; /* end position of tuning success */
185f63968baSMarek Vasut unsigned long ntap; /* temporary counter of tuning success */
186f63968baSMarek Vasut unsigned long match_cnt;/* counter of matching data */
187f63968baSMarek Vasut unsigned long i;
188f63968baSMarek Vasut bool select = false;
189f63968baSMarek Vasut u32 reg;
190f63968baSMarek Vasut
191f63968baSMarek Vasut /* Clear SCC_RVSREQ */
192cb0b6b03SMarek Vasut tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
193f63968baSMarek Vasut
194f63968baSMarek Vasut /* Merge the results */
195f63968baSMarek Vasut for (i = 0; i < tap_num * 2; i++) {
196f63968baSMarek Vasut if (!(taps & BIT(i))) {
197f63968baSMarek Vasut taps &= ~BIT(i % tap_num);
198f63968baSMarek Vasut taps &= ~BIT((i % tap_num) + tap_num);
199f63968baSMarek Vasut }
200f63968baSMarek Vasut if (!(smpcmp & BIT(i))) {
201f63968baSMarek Vasut smpcmp &= ~BIT(i % tap_num);
202f63968baSMarek Vasut smpcmp &= ~BIT((i % tap_num) + tap_num);
203f63968baSMarek Vasut }
204f63968baSMarek Vasut }
205f63968baSMarek Vasut
206f63968baSMarek Vasut /*
207f63968baSMarek Vasut * Find the longest consecutive run of successful probes. If that
208f63968baSMarek Vasut * is more than RENESAS_SDHI_MAX_TAP probes long then use the
209f63968baSMarek Vasut * center index as the tap.
210f63968baSMarek Vasut */
211f63968baSMarek Vasut tap_cnt = 0;
212f63968baSMarek Vasut ntap = 0;
213f63968baSMarek Vasut tap_start = 0;
214f63968baSMarek Vasut tap_end = 0;
215f63968baSMarek Vasut for (i = 0; i < tap_num * 2; i++) {
216f63968baSMarek Vasut if (taps & BIT(i))
217f63968baSMarek Vasut ntap++;
218f63968baSMarek Vasut else {
219f63968baSMarek Vasut if (ntap > tap_cnt) {
220f63968baSMarek Vasut tap_start = i - ntap;
221f63968baSMarek Vasut tap_end = i - 1;
222f63968baSMarek Vasut tap_cnt = ntap;
223f63968baSMarek Vasut }
224f63968baSMarek Vasut ntap = 0;
225f63968baSMarek Vasut }
226f63968baSMarek Vasut }
227f63968baSMarek Vasut
228f63968baSMarek Vasut if (ntap > tap_cnt) {
229f63968baSMarek Vasut tap_start = i - ntap;
230f63968baSMarek Vasut tap_end = i - 1;
231f63968baSMarek Vasut tap_cnt = ntap;
232f63968baSMarek Vasut }
233f63968baSMarek Vasut
234f63968baSMarek Vasut /*
235f63968baSMarek Vasut * If all of the TAP is OK, the sampling clock position is selected by
236f63968baSMarek Vasut * identifying the change point of data.
237f63968baSMarek Vasut */
238f63968baSMarek Vasut if (tap_cnt == tap_num * 2) {
239f63968baSMarek Vasut match_cnt = 0;
240f63968baSMarek Vasut ntap = 0;
241f63968baSMarek Vasut tap_start = 0;
242f63968baSMarek Vasut tap_end = 0;
243f63968baSMarek Vasut for (i = 0; i < tap_num * 2; i++) {
244f63968baSMarek Vasut if (smpcmp & BIT(i))
245f63968baSMarek Vasut ntap++;
246f63968baSMarek Vasut else {
247f63968baSMarek Vasut if (ntap > match_cnt) {
248f63968baSMarek Vasut tap_start = i - ntap;
249f63968baSMarek Vasut tap_end = i - 1;
250f63968baSMarek Vasut match_cnt = ntap;
251f63968baSMarek Vasut }
252f63968baSMarek Vasut ntap = 0;
253f63968baSMarek Vasut }
254f63968baSMarek Vasut }
255f63968baSMarek Vasut if (ntap > match_cnt) {
256f63968baSMarek Vasut tap_start = i - ntap;
257f63968baSMarek Vasut tap_end = i - 1;
258f63968baSMarek Vasut match_cnt = ntap;
259f63968baSMarek Vasut }
260f63968baSMarek Vasut if (match_cnt)
261f63968baSMarek Vasut select = true;
262f63968baSMarek Vasut } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
263f63968baSMarek Vasut select = true;
264f63968baSMarek Vasut
265f63968baSMarek Vasut if (select)
26695ead3d9SMarek Vasut priv->tap_set = ((tap_start + tap_end) / 2) % tap_num;
267f63968baSMarek Vasut else
268f63968baSMarek Vasut return -EIO;
269f63968baSMarek Vasut
270f63968baSMarek Vasut /* Set SCC */
27195ead3d9SMarek Vasut tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
272f63968baSMarek Vasut
273f63968baSMarek Vasut /* Enable auto re-tuning */
274cb0b6b03SMarek Vasut reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
275f63968baSMarek Vasut reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
276cb0b6b03SMarek Vasut tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
277f63968baSMarek Vasut
278f63968baSMarek Vasut return 0;
279f63968baSMarek Vasut }
280f63968baSMarek Vasut
renesas_sdhi_execute_tuning(struct udevice * dev,uint opcode)281f63968baSMarek Vasut int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
282f63968baSMarek Vasut {
283cb0b6b03SMarek Vasut struct tmio_sd_priv *priv = dev_get_priv(dev);
284f63968baSMarek Vasut struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
285f63968baSMarek Vasut struct mmc *mmc = upriv->mmc;
286f63968baSMarek Vasut unsigned int tap_num;
287f63968baSMarek Vasut unsigned int taps = 0, smpcmp = 0;
288f63968baSMarek Vasut int i, ret = 0;
289f63968baSMarek Vasut u32 caps;
290f63968baSMarek Vasut
291f63968baSMarek Vasut /* Only supported on Renesas RCar */
292cb0b6b03SMarek Vasut if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
293f63968baSMarek Vasut return -EINVAL;
294f63968baSMarek Vasut
295f63968baSMarek Vasut /* clock tuning is not needed for upto 52MHz */
296f63968baSMarek Vasut if (!((mmc->selected_mode == MMC_HS_200) ||
29750aa1d99SMarek Vasut (mmc->selected_mode == MMC_HS_400) ||
298f63968baSMarek Vasut (mmc->selected_mode == UHS_SDR104) ||
299f63968baSMarek Vasut (mmc->selected_mode == UHS_SDR50)))
300f63968baSMarek Vasut return 0;
301f63968baSMarek Vasut
302f63968baSMarek Vasut tap_num = renesas_sdhi_init_tuning(priv);
303f63968baSMarek Vasut if (!tap_num)
304f63968baSMarek Vasut /* Tuning is not supported */
305f63968baSMarek Vasut goto out;
306f63968baSMarek Vasut
307f63968baSMarek Vasut if (tap_num * 2 >= sizeof(taps) * 8) {
308f63968baSMarek Vasut dev_err(dev,
309f63968baSMarek Vasut "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
310f63968baSMarek Vasut goto out;
311f63968baSMarek Vasut }
312f63968baSMarek Vasut
313f63968baSMarek Vasut /* Issue CMD19 twice for each tap */
314f63968baSMarek Vasut for (i = 0; i < 2 * tap_num; i++) {
315f63968baSMarek Vasut renesas_sdhi_prepare_tuning(priv, i % tap_num);
316f63968baSMarek Vasut
317f63968baSMarek Vasut /* Force PIO for the tuning */
318f63968baSMarek Vasut caps = priv->caps;
319cb0b6b03SMarek Vasut priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
320f63968baSMarek Vasut
321f63968baSMarek Vasut ret = mmc_send_tuning(mmc, opcode, NULL);
322f63968baSMarek Vasut
323f63968baSMarek Vasut priv->caps = caps;
324f63968baSMarek Vasut
325f63968baSMarek Vasut if (ret == 0)
326f63968baSMarek Vasut taps |= BIT(i);
327f63968baSMarek Vasut
328f63968baSMarek Vasut ret = renesas_sdhi_compare_scc_data(priv);
329f63968baSMarek Vasut if (ret == 0)
330f63968baSMarek Vasut smpcmp |= BIT(i);
331f63968baSMarek Vasut
332f63968baSMarek Vasut mdelay(1);
333f63968baSMarek Vasut }
334f63968baSMarek Vasut
335f63968baSMarek Vasut ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
336f63968baSMarek Vasut
337f63968baSMarek Vasut out:
338f63968baSMarek Vasut if (ret < 0) {
339f63968baSMarek Vasut dev_warn(dev, "Tuning procedure failed\n");
340f63968baSMarek Vasut renesas_sdhi_reset_tuning(priv);
341f63968baSMarek Vasut }
342f63968baSMarek Vasut
343f63968baSMarek Vasut return ret;
344f63968baSMarek Vasut }
34550aa1d99SMarek Vasut #else
renesas_sdhi_hs400(struct udevice * dev)34650aa1d99SMarek Vasut static int renesas_sdhi_hs400(struct udevice *dev)
34750aa1d99SMarek Vasut {
34850aa1d99SMarek Vasut return 0;
34950aa1d99SMarek Vasut }
350f63968baSMarek Vasut #endif
351f63968baSMarek Vasut
renesas_sdhi_set_ios(struct udevice * dev)352f63968baSMarek Vasut static int renesas_sdhi_set_ios(struct udevice *dev)
353f63968baSMarek Vasut {
35450aa1d99SMarek Vasut struct tmio_sd_priv *priv = dev_get_priv(dev);
35550aa1d99SMarek Vasut u32 tmp;
35650aa1d99SMarek Vasut int ret;
35750aa1d99SMarek Vasut
35850aa1d99SMarek Vasut /* Stop the clock before changing its rate to avoid a glitch signal */
35950aa1d99SMarek Vasut tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
36050aa1d99SMarek Vasut tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
36150aa1d99SMarek Vasut tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
36250aa1d99SMarek Vasut
36350aa1d99SMarek Vasut ret = renesas_sdhi_hs400(dev);
36450aa1d99SMarek Vasut if (ret)
36550aa1d99SMarek Vasut return ret;
36650aa1d99SMarek Vasut
36750aa1d99SMarek Vasut ret = tmio_sd_set_ios(dev);
368cf39f3f3SMarek Vasut
369cf39f3f3SMarek Vasut mdelay(10);
370cf39f3f3SMarek Vasut
37150aa1d99SMarek Vasut #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
37250aa1d99SMarek Vasut CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
37350aa1d99SMarek Vasut CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
37450aa1d99SMarek Vasut struct mmc *mmc = mmc_get_mmc_dev(dev);
37550aa1d99SMarek Vasut if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
37650aa1d99SMarek Vasut (mmc->selected_mode != UHS_SDR104) &&
37750aa1d99SMarek Vasut (mmc->selected_mode != MMC_HS_200) &&
37850aa1d99SMarek Vasut (mmc->selected_mode != MMC_HS_400)) {
379f63968baSMarek Vasut renesas_sdhi_reset_tuning(priv);
38050aa1d99SMarek Vasut }
381f63968baSMarek Vasut #endif
382f63968baSMarek Vasut
383f63968baSMarek Vasut return ret;
384f63968baSMarek Vasut }
385f63968baSMarek Vasut
3862fc10754SMarek Vasut #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
renesas_sdhi_wait_dat0(struct udevice * dev,int state,int timeout)3872fc10754SMarek Vasut static int renesas_sdhi_wait_dat0(struct udevice *dev, int state, int timeout)
3882fc10754SMarek Vasut {
3892fc10754SMarek Vasut int ret = -ETIMEDOUT;
3902fc10754SMarek Vasut bool dat0_high;
3912fc10754SMarek Vasut bool target_dat0_high = !!state;
3922fc10754SMarek Vasut struct tmio_sd_priv *priv = dev_get_priv(dev);
3932fc10754SMarek Vasut
3942fc10754SMarek Vasut timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
3952fc10754SMarek Vasut while (timeout--) {
3962fc10754SMarek Vasut dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
3972fc10754SMarek Vasut if (dat0_high == target_dat0_high) {
3982fc10754SMarek Vasut ret = 0;
3992fc10754SMarek Vasut break;
4002fc10754SMarek Vasut }
4012fc10754SMarek Vasut udelay(10);
4022fc10754SMarek Vasut }
4032fc10754SMarek Vasut
4042fc10754SMarek Vasut return ret;
4052fc10754SMarek Vasut }
4062fc10754SMarek Vasut #endif
4072fc10754SMarek Vasut
408e94cad93SMarek Vasut static const struct dm_mmc_ops renesas_sdhi_ops = {
409cb0b6b03SMarek Vasut .send_cmd = tmio_sd_send_cmd,
410f63968baSMarek Vasut .set_ios = renesas_sdhi_set_ios,
411cb0b6b03SMarek Vasut .get_cd = tmio_sd_get_cd,
41250aa1d99SMarek Vasut #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
41350aa1d99SMarek Vasut CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
41450aa1d99SMarek Vasut CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
415f63968baSMarek Vasut .execute_tuning = renesas_sdhi_execute_tuning,
416f63968baSMarek Vasut #endif
4172fc10754SMarek Vasut #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
4182fc10754SMarek Vasut .wait_dat0 = renesas_sdhi_wait_dat0,
4192fc10754SMarek Vasut #endif
420e94cad93SMarek Vasut };
421e94cad93SMarek Vasut
422cb0b6b03SMarek Vasut #define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
423f98833dbSMarek Vasut #define RENESAS_GEN3_QUIRKS \
424cb0b6b03SMarek Vasut TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
425f98833dbSMarek Vasut
426e94cad93SMarek Vasut static const struct udevice_id renesas_sdhi_match[] = {
427f98833dbSMarek Vasut { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
428f98833dbSMarek Vasut { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
429f98833dbSMarek Vasut { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
430f98833dbSMarek Vasut { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
431f98833dbSMarek Vasut { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
432f98833dbSMarek Vasut { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
433f98833dbSMarek Vasut { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
434f98833dbSMarek Vasut { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
435f98833dbSMarek Vasut { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
436d629152aSMarek Vasut { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
437f98833dbSMarek Vasut { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
438e94cad93SMarek Vasut { /* sentinel */ }
439e94cad93SMarek Vasut };
440e94cad93SMarek Vasut
renesas_sdhi_clk_get_rate(struct tmio_sd_priv * priv)4418ec6a04bSMarek Vasut static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
4428ec6a04bSMarek Vasut {
4438ec6a04bSMarek Vasut return clk_get_rate(&priv->clk);
4448ec6a04bSMarek Vasut }
4458ec6a04bSMarek Vasut
renesas_sdhi_filter_caps(struct udevice * dev)446d34bd2deSMarek Vasut static void renesas_sdhi_filter_caps(struct udevice *dev)
447d34bd2deSMarek Vasut {
448d34bd2deSMarek Vasut struct tmio_sd_plat *plat = dev_get_platdata(dev);
449d34bd2deSMarek Vasut struct tmio_sd_priv *priv = dev_get_priv(dev);
450d34bd2deSMarek Vasut
451d34bd2deSMarek Vasut if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
452d34bd2deSMarek Vasut return;
453d34bd2deSMarek Vasut
454d34bd2deSMarek Vasut /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1 */
455d34bd2deSMarek Vasut if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
456d34bd2deSMarek Vasut (rmobile_get_cpu_rev_integer() <= 1)) ||
457d34bd2deSMarek Vasut ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
458d34bd2deSMarek Vasut (rmobile_get_cpu_rev_integer() == 1) &&
459d34bd2deSMarek Vasut (rmobile_get_cpu_rev_fraction() <= 1)))
460d34bd2deSMarek Vasut plat->cfg.host_caps &= ~MMC_MODE_HS400;
46150aa1d99SMarek Vasut
46250aa1d99SMarek Vasut /* H3 ES2.0 uses 4 tuning taps */
46350aa1d99SMarek Vasut if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
46450aa1d99SMarek Vasut (rmobile_get_cpu_rev_integer() == 2))
46550aa1d99SMarek Vasut priv->nrtaps = 4;
46650aa1d99SMarek Vasut else
46750aa1d99SMarek Vasut priv->nrtaps = 8;
468992bcf4fSMarek Vasut
469992bcf4fSMarek Vasut /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
470992bcf4fSMarek Vasut if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
471992bcf4fSMarek Vasut (rmobile_get_cpu_rev_integer() <= 1)) ||
472992bcf4fSMarek Vasut ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
473992bcf4fSMarek Vasut (rmobile_get_cpu_rev_integer() == 1) &&
474992bcf4fSMarek Vasut (rmobile_get_cpu_rev_fraction() == 0)))
475992bcf4fSMarek Vasut priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
476992bcf4fSMarek Vasut else
477992bcf4fSMarek Vasut priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
478d34bd2deSMarek Vasut }
479d34bd2deSMarek Vasut
renesas_sdhi_probe(struct udevice * dev)480c769e609SMarek Vasut static int renesas_sdhi_probe(struct udevice *dev)
481c769e609SMarek Vasut {
48230b5d9aaSMasahiro Yamada struct tmio_sd_priv *priv = dev_get_priv(dev);
483c769e609SMarek Vasut u32 quirks = dev_get_driver_data(dev);
4847cf7ef81SMarek Vasut struct fdt_resource reg_res;
4857cf7ef81SMarek Vasut DECLARE_GLOBAL_DATA_PTR;
4867cf7ef81SMarek Vasut int ret;
4877cf7ef81SMarek Vasut
4888ec6a04bSMarek Vasut priv->clk_get_rate = renesas_sdhi_clk_get_rate;
4898ec6a04bSMarek Vasut
490f98833dbSMarek Vasut if (quirks == RENESAS_GEN2_QUIRKS) {
491f98833dbSMarek Vasut ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
492f98833dbSMarek Vasut "reg", 0, ®_res);
4937cf7ef81SMarek Vasut if (ret < 0) {
494f98833dbSMarek Vasut dev_err(dev, "\"reg\" resource not found, ret=%i\n",
495f98833dbSMarek Vasut ret);
4967cf7ef81SMarek Vasut return ret;
4977cf7ef81SMarek Vasut }
4987cf7ef81SMarek Vasut
499f98833dbSMarek Vasut if (fdt_resource_size(®_res) == 0x100)
500cb0b6b03SMarek Vasut quirks |= TMIO_SD_CAP_16BIT;
501f98833dbSMarek Vasut }
502c769e609SMarek Vasut
5038ec6a04bSMarek Vasut ret = clk_get_by_index(dev, 0, &priv->clk);
50430b5d9aaSMasahiro Yamada if (ret < 0) {
50530b5d9aaSMasahiro Yamada dev_err(dev, "failed to get host clock\n");
50630b5d9aaSMasahiro Yamada return ret;
50730b5d9aaSMasahiro Yamada }
50830b5d9aaSMasahiro Yamada
50930b5d9aaSMasahiro Yamada /* set to max rate */
5108ec6a04bSMarek Vasut ret = clk_set_rate(&priv->clk, 200000000);
5118ec6a04bSMarek Vasut if (ret < 0) {
51230b5d9aaSMasahiro Yamada dev_err(dev, "failed to set rate for host clock\n");
5138ec6a04bSMarek Vasut clk_free(&priv->clk);
5148ec6a04bSMarek Vasut return ret;
51530b5d9aaSMasahiro Yamada }
51630b5d9aaSMasahiro Yamada
5178ec6a04bSMarek Vasut ret = clk_enable(&priv->clk);
51830b5d9aaSMasahiro Yamada if (ret) {
51930b5d9aaSMasahiro Yamada dev_err(dev, "failed to enable host clock\n");
52030b5d9aaSMasahiro Yamada return ret;
52130b5d9aaSMasahiro Yamada }
52230b5d9aaSMasahiro Yamada
523cb0b6b03SMarek Vasut ret = tmio_sd_probe(dev, quirks);
524d34bd2deSMarek Vasut
525d34bd2deSMarek Vasut renesas_sdhi_filter_caps(dev);
526d34bd2deSMarek Vasut
52750aa1d99SMarek Vasut #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
52850aa1d99SMarek Vasut CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
52950aa1d99SMarek Vasut CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
53052e17968SMarek Vasut if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
53165186977SMarek Vasut renesas_sdhi_reset_tuning(priv);
532f63968baSMarek Vasut #endif
533f63968baSMarek Vasut return ret;
534c769e609SMarek Vasut }
535c769e609SMarek Vasut
536e94cad93SMarek Vasut U_BOOT_DRIVER(renesas_sdhi) = {
537e94cad93SMarek Vasut .name = "renesas-sdhi",
538e94cad93SMarek Vasut .id = UCLASS_MMC,
539e94cad93SMarek Vasut .of_match = renesas_sdhi_match,
540cb0b6b03SMarek Vasut .bind = tmio_sd_bind,
541c769e609SMarek Vasut .probe = renesas_sdhi_probe,
542cb0b6b03SMarek Vasut .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
543cb0b6b03SMarek Vasut .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
544e94cad93SMarek Vasut .ops = &renesas_sdhi_ops,
545e94cad93SMarek Vasut };
546