| /openbmc/linux/drivers/spi/ |
| H A D | spi-bcm-qspi.c | 25 #include "spi-bcm-qspi.h"
255 static inline bool has_bspi(struct bcm_qspi *qspi) in has_bspi() argument
257 return qspi->bspi_mode; in has_bspi()
261 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) in bcm_qspi_has_fastbr() argument
263 if (!has_bspi(qspi) && in bcm_qspi_has_fastbr()
264 ((qspi->mspi_maj_rev >= 1) && in bcm_qspi_has_fastbr()
265 (qspi->mspi_min_rev >= 5))) in bcm_qspi_has_fastbr()
272 static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi) in bcm_qspi_has_sysclk_108() argument
274 if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk || in bcm_qspi_has_sysclk_108()
275 ((qspi->mspi_maj_rev >= 1) && in bcm_qspi_has_sysclk_108()
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| H A D | spi-ti-qspi.c | 3 * TI QSPI driver
126 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, in ti_qspi_read() argument
129 return readl(qspi->base + reg); in ti_qspi_read()
132 static inline void ti_qspi_write(struct ti_qspi *qspi, in ti_qspi_write() argument
135 writel(val, qspi->base + reg); in ti_qspi_write()
140 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_setup() local
144 dev_dbg(qspi->dev, "master busy doing other transfers\n"); in ti_qspi_setup()
148 if (!qspi->master->max_speed_hz) { in ti_qspi_setup()
149 dev_err(qspi->dev, "spi max frequency not defined\n"); in ti_qspi_setup()
153 spi->max_speed_hz = min(spi->max_speed_hz, qspi->master->max_speed_hz); in ti_qspi_setup()
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| H A D | spi-stm32-qspi.c | 131 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id; in stm32_qspi_irq() local
134 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
135 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
140 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
141 complete(&qspi->match_completion); in stm32_qspi_irq()
149 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
150 complete(&qspi->data_completion); in stm32_qspi_irq()
166 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi, in stm32_qspi_tx_poll() argument
184 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, in stm32_qspi_tx_poll()
188 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n", in stm32_qspi_tx_poll()
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| H A D | spi-microchip-core-qspi.c | 3 * Microchip coreQSPI QSPI controller driver
25 * QSPI Control register mask defines
43 * QSPI Frames register mask defines
55 * QSPI Interrupt Enable register mask defines
65 * QSPI Status register mask defines
84 /* QSPI ready time out value */
88 * QSPI Register offsets.
103 * struct mchp_coreqspi - Defines qspi driver instance
104 * @regs: Virtual address of the QSPI controller registers
105 * @clk: QSPI Operating clock
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| H A D | spi-zynq-qspi.c | 41 * QSPI Configuration Register bit Masks
44 * of the QSPI controller
57 * QSPI Configuration Register - Baud rate and slave select
67 * QSPI Interrupt Registers bit Masks
72 #define ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK BIT(0) /* QSPI RX FIFO Overflow */
73 #define ZYNQ_QSPI_IXR_TXNFULL_MASK BIT(2) /* QSPI TX FIFO Overflow */
74 #define ZYNQ_QSPI_IXR_TXFULL_MASK BIT(3) /* QSPI TX FIFO is full */
75 #define ZYNQ_QSPI_IXR_RXNEMTY_MASK BIT(4) /* QSPI RX FIFO Not Empty */
76 #define ZYNQ_QSPI_IXR_RXF_FULL_MASK BIT(5) /* QSPI RX FIFO is full */
77 #define ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK BIT(6) /* QSPI TX FIFO Underflow */
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | ti_qspi.txt | 1 TI QSPI controller.
4 - compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".
5 - reg: Should contain QSPI registers location and length.
7 - qspi_base: Qspi configuration register Address space
10 - interrupts: should contain the qspi interrupt number.
12 - ti,hwmods: Name of the hwmod associated to the QSPI
19 - syscon-chipselects: Handle to system control region contains QSPI
22 NOTE: TI QSPI controller requires different pinmux and IODelay
26 specified in the slave nodes of TI QSPI controller without appropriate
32 qspi: qspi@47900000 {
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| H A D | cdns,qspi-nor.yaml | 4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
26 const: starfive,jh7110-qspi
37 enum: [ qspi, qspi-ocp, rstc_ref ]
48 enum: [ qspi, qspi-ocp ]
53 const: amd,pensando-elba-qspi
70 - amd,pensando-elba-qspi
71 - ti,k2g-qspi
73 - intel,lgm-qspi
75 - intel,socfpga-qspi
76 - starfive,jh7110-qspi
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| H A D | fsl,spi-fsl-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#
19 - fsl,vf610-qspi
20 - fsl,imx6sx-qspi
21 - fsl,imx7d-qspi
22 - fsl,imx6ul-qspi
23 - fsl,ls1021a-qspi
24 - fsl,ls2080a-qspi
27 - fsl,ls1043a-qspi
28 - const: fsl,ls1021a-qspi
31 - fsl,imx8mq-qspi
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| H A D | qcom,spi-qcom-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
7 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
12 description: The QSPI controller allows SPI protocol communication in single,
23 - qcom,sc7180-qspi
24 - qcom,sc7280-qspi
25 - qcom,sdm845-qspi
27 - const: qcom,qspi-v1
46 - description: QSPI core clock
55 - const: qspi-config
56 - const: qspi-memory
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| H A D | renesas,rspi.yaml | 7 title: Renesas (Quad) Serial Peripheral Interface (RSPI/QSPI)
31 - renesas,qspi-r8a7742 # RZ/G1H
32 - renesas,qspi-r8a7743 # RZ/G1M
33 - renesas,qspi-r8a7744 # RZ/G1N
34 - renesas,qspi-r8a7745 # RZ/G1E
35 - renesas,qspi-r8a77470 # RZ/G1C
36 - renesas,qspi-r8a7790 # R-Car H2
37 - renesas,qspi-r8a7791 # R-Car M2-W
38 - renesas,qspi-r8a7792 # R-Car V2H
39 - renesas,qspi-r8a7793 # R-Car M2-N
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| H A D | brcm,spi-bcm-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
36 - brcm,spi-bcm7425-qspi
37 - brcm,spi-bcm7429-qspi
38 - brcm,spi-bcm7435-qspi
39 - brcm,spi-bcm7445-qspi
40 - brcm,spi-bcm7216-qspi
41 - brcm,spi-bcm7278-qspi
42 - const: brcm,spi-bcm-qspi
47 - brcm,spi-brcmstb-qspi
49 - brcm,spi-nsp-qspi
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| H A D | nvidia,tegra210-quad.yaml | 19 - nvidia,tegra210-qspi
20 - nvidia,tegra186-qspi
21 - nvidia,tegra194-qspi
22 - nvidia,tegra234-qspi
23 - nvidia,tegra241-qspi
33 - const: qspi
77 compatible = "nvidia,tegra210-qspi";
84 clock-names = "qspi", "qspi_out";
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | zynq-cse-qspi.dtsi | 3 * Xilinx CSE QSPI board DTS
12 model = "Zynq CSE QSPI Board";
13 compatible = "xlnx,zynq-cse-qspi", "xlnx,zynq-7000";
16 spi0 = &qspi;
51 qspi: spi@e000d000 { label
54 compatible = "xlnx,zynq-qspi-1.0";
70 partition@qspi-fsbl-uboot {
71 label = "qspi-fsbl-uboot";
74 partition@qspi-linux {
75 label = "qspi-linux";
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| H A D | zynq-topic-miami.dts | 16 spi0 = &qspi;
33 &qspi {
47 partition@qspi-u-boot-spl {
48 label = "qspi-u-boot-spl";
51 partition@qspi-u-boot-img {
52 label = "qspi-u-boot-img";
55 partition@qspi-device-tree {
56 label = "qspi-device-tree";
59 partition@qspi-linux {
60 label = "qspi-linux";
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| H A D | zynqmp-zc1254-revA.dts | 23 spi0 = &qspi;
41 &qspi {
51 partition@qspi-fsbl-uboot { /* for testing purpose */
52 label = "qspi-fsbl-uboot";
55 partition@qspi-linux { /* for testing purpose */
56 label = "qspi-linux";
59 partition@qspi-device-tree { /* for testing purpose */
60 label = "qspi-device-tree";
63 partition@qspi-rootfs { /* for testing purpose */
64 label = "qspi-rootfs";
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| H A D | zynqmp-zc1275-revA.dts | 23 spi0 = &qspi;
41 &qspi {
51 partition@qspi-fsbl-uboot { /* for testing purpose */
52 label = "qspi-fsbl-uboot";
55 partition@qspi-linux { /* for testing purpose */
56 label = "qspi-linux";
59 partition@qspi-device-tree { /* for testing purpose */
60 label = "qspi-device-tree";
63 partition@qspi-rootfs { /* for testing purpose */
64 label = "qspi-rootfs";
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| H A D | zynqmp-zc1275-revB.dts | 23 spi0 = &qspi;
42 &qspi {
52 partition@qspi-fsbl-uboot { /* for testing purpose */
53 label = "qspi-fsbl-uboot";
56 partition@qspi-linux { /* for testing purpose */
57 label = "qspi-linux";
60 partition@qspi-device-tree { /* for testing purpose */
61 label = "qspi-device-tree";
64 partition@qspi-rootfs { /* for testing purpose */
65 label = "qspi-rootfs";
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| H A D | zynqmp-zc1232-revA.dts | 23 spi0 = &qspi;
41 &qspi {
51 partition@qspi-fsbl-uboot { /* for testing purpose */
52 label = "qspi-fsbl-uboot";
55 partition@qspi-linux { /* for testing purpose */
56 label = "qspi-linux";
59 partition@qspi-device-tree { /* for testing purpose */
60 label = "qspi-device-tree";
63 partition@qspi-rootfs { /* for testing purpose */
64 label = "qspi-rootfs";
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| H A D | keystone-k2g-ice.dts | 37 &qspi {
55 label = "QSPI.u-boot";
59 label = "QSPI.u-boot-env";
63 label = "QSPI.skern";
67 label = "QSPI.pmmc-firmware";
71 label = "QSPI.kernel";
75 label = "QSPI.u-boot-spl-os";
79 label = "QSPI.file-system";
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| H A D | zynqmp-zc1751-xm018-dc4.dts | 32 spi0 = &qspi;
180 &qspi {
190 partition@qspi-fsbl-uboot { /* for testing purpose */
191 label = "qspi-fsbl-uboot";
194 partition@qspi-linux { /* for testing purpose */
195 label = "qspi-linux";
198 partition@qspi-device-tree { /* for testing purpose */
199 label = "qspi-device-tree";
202 partition@qspi-rootfs { /* for testing purpose */
203 label = "qspi-rootfs";
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| /openbmc/u-boot/board/freescale/ls1012ardb/ |
| H A D | README | 22 -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
24 - QSPI NOR flash memory (2 virtual banks)
25 - the QSPI emulator.s
42 a) QSPI Flash Emu Boot
43 b) QSPI Flash 1
44 c) QSPI Flash 2
46 QSPI flash map
48 Images | Size |QSPI Flash Address
63 -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
65 - QSPI NOR flash memory
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.qspi | 1 QSPI Boot source support Overview
14 Booting from QSPI
16 Booting from QSPI requires two images, RCW and u-boot-dtb.bin.
17 The difference between QSPI boot RCW image and NOR boot image is the PBI
19 to the address for u-boot in QSPI flash.
21 RCW image should be written to the beginning of QSPI flash device.
31 To get the QSPI image, build u-boot with QSPI config, for example,
42 With these two images in QSPI flash device, the board can boot from QSPI.
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| /openbmc/u-boot/drivers/spi/ |
| H A D | Kconfig | 99 bool "Cadence QSPI driver"
101 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
158 bool "Mediatek QSPI driver"
161 Enable the Mediatek QSPI driver. This driver can be
163 Mediatek QSPI IP core.
239 bool "STM32F7 QSPI driver"
243 Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be
272 bool "nVidia Tegra210 QSPI driver"
274 Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver
295 bool "Zynq QSPI driver"
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| /openbmc/u-boot/board/freescale/ls1012aqds/ |
| H A D | README | 22 - QSPI Controller
23 - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
24 signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
47 a) QSPI Flash Emu Boot
48 b) QSPI Flash 1
49 c) QSPI Flash 2
51 QSPI flash map
53 Images | Size |QSPI Flash Address
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| /openbmc/linux/arch/m68k/include/asm/ |
| H A D | mcfqspi.h | 3 * Definitions for Freescale Coldfire QSPI module
12 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
18 * The QSPI module has 4 hardware chip selects. We don't use them. Instead
20 * platform data for each QSPI master controller. Only the select and
31 * struct mcfqspi_platform_data - platform data for the coldfire qspi driver
32 * @bus_num: board specific identifier for this qspi driver.
33 * @num_chipselects: number of chip selects supported by this qspi driver.
|