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/openbmc/linux/drivers/clocksource/
H A Dsamsung_pwm_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * samsung - Common hr-timer support (s3c and s5p)
29 #define REG_TCFG0 0x00
30 #define REG_TCFG1 0x04
31 #define REG_TCON 0x08
32 #define REG_TINT_CSTAT 0x44
34 #define REG_TCNTB(chan) (0x0c + 12 * (chan))
35 #define REG_TCMPB(chan) (0x10 + 12 * (chan))
37 #define TCFG0_PRESCALER_MASK 0xff
41 #define TCFG1_MUX_MASK 0xf
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/openbmc/linux/drivers/pwm/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2011-2012 Avionic Design GmbH
12 #include <linux/pwm.h>
21 #include <dt-bindings/pwm/pwm.h>
24 #include <trace/events/pwm.h>
42 start = bitmap_find_next_zero_area(allocated_pwms, MAX_PWMS, 0, in alloc_pwms()
43 count, 0); in alloc_pwms()
46 return -ENOSPC; in alloc_pwms()
56 bitmap_clear(allocated_pwms, chip->base, chip->npwm); in free_pwms()
58 kfree(chip->pwms); in free_pwms()
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H A Dpwm-twl.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/pwm.h>
22 #define TWL_PWM_MAX 0x7f
25 #define TWL4030_GPBR1_REG 0x0c
26 #define TWL4030_PMBR1_REG 0x0d
29 #define TWL4030_PWMXCLK_ENABLE (1 << 0)
32 #define TWL4030_PWM_TOGGLE(pwm, x) ((x) << (pwm)) argument
35 #define TWL4030_GPIO6_PWM0_MUTE_MASK (0x03 << 2)
36 #define TWL4030_GPIO6_PWM0_MUTE_PWM0 (0x01 << 2)
37 #define TWL4030_GPIO7_VIBRASYNC_PWM1_MASK (0x03 << 4)
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H A Dsysfs.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * A simple sysfs interface for the generic PWM framework
15 #include <linux/pwm.h>
19 struct pwm_device *pwm; member
33 return export->pwm; in child_to_pwm_device()
40 const struct pwm_device *pwm = child_to_pwm_device(child); in period_show() local
43 pwm_get_state(pwm, &state); in period_show()
53 struct pwm_device *pwm = export->pwm; in period_store() local
58 ret = kstrtou64(buf, 0, &val); in period_store()
62 mutex_lock(&export->lock); in period_store()
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H A Dpwm-twl-led.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * This driver is a complete rewrite of the former pwm-twl6030.c authorded by:
15 * - The twl6030 hardware only supports two period lengths (128 clock ticks and
17 * - The hardware doesn't support ON = 0, so the active part of a period doesn't
19 * - The hardware could support inverted polarity (with a similar limitation as
21 * - The hardware emits a constant low output when disabled.
22 * - A request for .duty_cycle = 0 results in an output wave with one active
24 * - The driver only implements setting the relative duty cycle.
25 * - The driver doesn't implement .get_state().
31 #include <linux/pwm.h>
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H A Dpwm-vt8500.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/pwm/pwm-vt8500.c
16 #include <linux/pwm.h>
28 #define REG_CTRL(pwm) (((pwm) << 4) + 0x00) argument
29 #define REG_SCALAR(pwm) (((pwm) << 4) + 0x04) argument
30 #define REG_PERIOD(pwm) (((pwm) << 4) + 0x08) argument
31 #define REG_DUTY(pwm) (((pwm) << 4) + 0x0C) argument
32 #define REG_STATUS 0x40
34 #define CTRL_ENABLE BIT(0)
41 #define STATUS_CTRL_UPDATE BIT(0)
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H A Dpwm-stmpe.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/pwm.h>
18 #define STMPE24XX_PWMCS 0x30
19 #define PWMCS_EN_PWM0 BIT(0)
22 #define STMPE24XX_PWMIC0 0x38
23 #define STMPE24XX_PWMIC1 0x39
24 #define STMPE24XX_PWMIC2 0x3a
39 static int stmpe_24xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in stmpe_24xx_pwm_enable() argument
45 ret = stmpe_reg_read(stmpe_pwm->stmpe, STMPE24XX_PWMCS); in stmpe_24xx_pwm_enable()
46 if (ret < 0) { in stmpe_24xx_pwm_enable()
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H A Dpwm-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <linux/pwm.h>
22 /* PWM registers and bits definitions */
23 #define PWMCON 0x00
24 #define PWMHDUR 0x04
25 #define PWMLDUR 0x08
26 #define PWMGDUR 0x0c
27 #define PWMWAVENUM 0x28
28 #define PWMDWIDTH 0x2c
29 #define PWM45DWIDTH_FIXUP 0x30
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H A Dpwm-samsung.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
9 * PWM driver for Samsung SoCs
21 #include <linux/pwm.h>
29 #define REG_TCFG0 0x00
30 #define REG_TCFG1 0x04
31 #define REG_TCON 0x08
33 #define REG_TCNTB(chan) (0x0c + ((chan) * 0xc))
34 #define REG_TCMPB(chan) (0x10 + ((chan) * 0xc))
36 #define TCFG0_PRESCALER_MASK 0xff
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H A Dpwm-lpss.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Low Power Subsystem PWM controller driver
24 #include "pwm-lpss.h"
26 #define PWM 0x00000000 macro
30 #define PWM_ON_TIME_DIV_MASK GENMASK(7, 0)
32 /* Size of each PWM register space if multiple */
33 #define PWM_SIZE 0x400
74 static inline u32 pwm_lpss_read(const struct pwm_device *pwm) in pwm_lpss_read() argument
76 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); in pwm_lpss_read()
78 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); in pwm_lpss_read()
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H A Dpwm-jz4740.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
7 * - The .apply callback doesn't complete the currently running period before
15 #include <linux/mfd/ingenic-tcu.h>
20 #include <linux/pwm.h>
40 /* Enable all TCU channels for PWM use by default except channels 0/1 */ in jz4740_pwm_can_use_chn()
41 u32 pwm_channels_mask = GENMASK(jz->chip.npwm - 1, 2); in jz4740_pwm_can_use_chn()
43 device_property_read_u32(jz->chip.dev->parent, in jz4740_pwm_can_use_chn()
44 "ingenic,pwm-channels-mask", in jz4740_pwm_can_use_chn()
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H A Dpwm-hibvt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PWM Controller Driver for HiSilicon BVT SoCs
15 #include <linux/pwm.h>
18 #define PWM_CFG0_ADDR(x) (((x) * 0x20) + 0x0)
19 #define PWM_CFG1_ADDR(x) (((x) * 0x20) + 0x4)
20 #define PWM_CFG2_ADDR(x) (((x) * 0x20) + 0x8)
21 #define PWM_CTRL_ADDR(x) (((x) * 0x20) + 0xC)
23 #define PWM_ENABLE_SHIFT 0
24 #define PWM_ENABLE_MASK BIT(0)
32 #define PWM_PERIOD_MASK GENMASK(31, 0)
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/openbmc/u-boot/doc/device-tree-bindings/pwm/
H A Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
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/openbmc/linux/include/linux/
H A Dpwm.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * enum pwm_polarity - polarity of a PWM signal
13 * @PWM_POLARITY_NORMAL: a high signal for the duration of the duty-
16 * @PWM_POLARITY_INVERSED: a low signal for the duration of the duty-
26 * struct pwm_args - board-dependent PWM arguments
30 * This structure describes board-dependent arguments attached to a PWM
31 * device. These arguments are usually retrieved from the PWM lookup table or
34 * Do not confuse this with the PWM state: PWM arguments represent the initial
35 * configuration that users want to use on this PWM device rather than the
36 * current PWM hardware state.
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/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-samsung.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC PWM timers
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
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H A Drenesas,pwm-rcar.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car PWM Timer Controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,pwm-r8a7742 # RZ/G1H
17 - renesas,pwm-r8a7743 # RZ/G1M
18 - renesas,pwm-r8a7744 # RZ/G1N
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H A Dallwinner,sun4i-a10-pwm.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/allwinner,sun4i-a10-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 PWM
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#pwm-cells":
19 - const: allwinner,sun4i-a10-pwm
20 - const: allwinner,sun5i-a10s-pwm
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H A Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
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H A Dpwm-lp3943.txt1 TI/National Semiconductor LP3943 PWM controller
4 - compatible: "ti,lp3943-pwm"
5 - #pwm-cells: Should be 2. See pwm.yaml in this directory for a
9 - ti,pwm0 or ti,pwm1: Output pin number(s) for PWM channel 0 or 1.
10 0 = output 0
17 PWM 0 is for RGB LED brightness control
18 PWM 1 is for brightness control of LP8557 backlight device
23 reg = <0x60>;
26 * PWM 0 : output 8, 9 and 10
27 * PWM 1 : output 15
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/openbmc/u-boot/include/
H A Dpwm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * header file for pwm driver.
13 /* struct pwm_ops: Operations for the PWM uclass */
16 * set_config() - Set the PWM configuration
18 * @dev: PWM device to update
19 * @channel: PWM channel to update
20 * @period_ns: PWM period in nanoseconds
21 * @duty_ns: PWM duty period in nanoseconds
22 * @return 0 if OK, -ve on error
28 * set_enable() - Enable or disable the PWM
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/openbmc/linux/Documentation/hwmon/
H A Ddme1737.rst10 Addresses scanned: I2C 0x2c, 0x2d, 0x2e
18 Addresses scanned: none, address read from Super-I/O config space
26 Addresses scanned: I2C 0x2c, 0x2d, 0x2e
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
47 and PWM output control functions. Using this parameter
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
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/openbmc/linux/drivers/input/keyboard/
H A Dlm8323.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2009 Nokia Corporation
26 #define LM8323_CMD_READ_ID 0x80 /* Read chip ID. */
27 #define LM8323_CMD_WRITE_CFG 0x81 /* Set configuration item. */
28 #define LM8323_CMD_READ_INT 0x82 /* Get interrupt status. */
29 #define LM8323_CMD_RESET 0x83 /* Reset, same as external one */
30 #define LM8323_CMD_WRITE_PORT_SEL 0x85 /* Set GPIO in/out. */
31 #define LM8323_CMD_WRITE_PORT_STATE 0x86 /* Set GPIO pullup. */
32 #define LM8323_CMD_READ_PORT_SEL 0x87 /* Get GPIO in/out. */
33 #define LM8323_CMD_READ_PORT_STATE 0x88 /* Get GPIO pullup. */
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/openbmc/linux/Documentation/devicetree/bindings/hwmon/
H A Dnpcm750-pwm-fan.txt1 Nuvoton NPCM PWM and Fan Tacho controller device
3 The Nuvoton BMC NPCM7XX supports 8 Pulse-width modulation (PWM)
6 The Nuvoton BMC NPCM8XX supports 12 Pulse-width modulation (PWM)
9 Required properties for pwm-fan node
10 - #address-cells : should be 1.
11 - #size-cells : should be 0.
12 - compatible : "nuvoton,npcm750-pwm-fan" for Poleg NPCM7XX.
13 : "nuvoton,npcm845-pwm-fan" for Arbel NPCM8XX.
14 - reg : specifies physical base address and size of the registers.
15 - reg-names : must contain:
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dnvidia,tegra124-dfll.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
18 - registers for the I2C output logic.
19 - registers for the integrated I2C master controller.
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/openbmc/u-boot/arch/arm/cpu/armv7/s5p-common/
H A Dpwm.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <pwm.h>
12 #include <asm/arch/pwm.h>
17 const struct s5p_timer *pwm = in pwm_enable() local
21 tcon = readl(&pwm->tcon); in pwm_enable()
24 writel(tcon, &pwm->tcon); in pwm_enable()
26 return 0; in pwm_enable()
31 const struct s5p_timer *pwm = in pwm_disable() local
35 tcon = readl(&pwm->tcon); in pwm_disable()
38 writel(tcon, &pwm->tcon); in pwm_disable()
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