19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2a245ccebSSascha Hauer /*
3261995ddSAxel Lin * drivers/pwm/pwm-vt8500.c
4a245ccebSSascha Hauer *
563e1ed23STony Prisk * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6a245ccebSSascha Hauer * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
7a245ccebSSascha Hauer */
8a245ccebSSascha Hauer
90a41b0c5SRob Herring #include <linux/mod_devicetable.h>
10a245ccebSSascha Hauer #include <linux/module.h>
11a245ccebSSascha Hauer #include <linux/kernel.h>
12a245ccebSSascha Hauer #include <linux/platform_device.h>
13a245ccebSSascha Hauer #include <linux/slab.h>
14a245ccebSSascha Hauer #include <linux/err.h>
15a245ccebSSascha Hauer #include <linux/io.h>
16a245ccebSSascha Hauer #include <linux/pwm.h>
17a245ccebSSascha Hauer #include <linux/delay.h>
1863e1ed23STony Prisk #include <linux/clk.h>
19a245ccebSSascha Hauer
20a245ccebSSascha Hauer #include <asm/div64.h>
21a245ccebSSascha Hauer
2263e1ed23STony Prisk /*
2363e1ed23STony Prisk * SoC architecture allocates register space for 4 PWMs but only
2463e1ed23STony Prisk * 2 are currently implemented.
2563e1ed23STony Prisk */
2663e1ed23STony Prisk #define VT8500_NR_PWMS 2
27a245ccebSSascha Hauer
288ab432caSTony Prisk #define REG_CTRL(pwm) (((pwm) << 4) + 0x00)
298ab432caSTony Prisk #define REG_SCALAR(pwm) (((pwm) << 4) + 0x04)
308ab432caSTony Prisk #define REG_PERIOD(pwm) (((pwm) << 4) + 0x08)
318ab432caSTony Prisk #define REG_DUTY(pwm) (((pwm) << 4) + 0x0C)
328ab432caSTony Prisk #define REG_STATUS 0x40
338ab432caSTony Prisk
348ab432caSTony Prisk #define CTRL_ENABLE BIT(0)
358ab432caSTony Prisk #define CTRL_INVERT BIT(1)
368ab432caSTony Prisk #define CTRL_AUTOLOAD BIT(2)
378ab432caSTony Prisk #define CTRL_STOP_IMM BIT(3)
388ab432caSTony Prisk #define CTRL_LOAD_PRESCALE BIT(4)
398ab432caSTony Prisk #define CTRL_LOAD_PERIOD BIT(5)
408ab432caSTony Prisk
418ab432caSTony Prisk #define STATUS_CTRL_UPDATE BIT(0)
428ab432caSTony Prisk #define STATUS_SCALAR_UPDATE BIT(1)
438ab432caSTony Prisk #define STATUS_PERIOD_UPDATE BIT(2)
448ab432caSTony Prisk #define STATUS_DUTY_UPDATE BIT(3)
458ab432caSTony Prisk #define STATUS_ALL_UPDATE 0x0F
468ab432caSTony Prisk
47a245ccebSSascha Hauer struct vt8500_chip {
48a245ccebSSascha Hauer struct pwm_chip chip;
49a245ccebSSascha Hauer void __iomem *base;
5063e1ed23STony Prisk struct clk *clk;
51a245ccebSSascha Hauer };
52a245ccebSSascha Hauer
53a245ccebSSascha Hauer #define to_vt8500_chip(chip) container_of(chip, struct vt8500_chip, chip)
54a245ccebSSascha Hauer
55a245ccebSSascha Hauer #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
vt8500_pwm_busy_wait(struct vt8500_chip * vt8500,int nr,u8 bitmask)56e9d866d5SUwe Kleine-König static inline void vt8500_pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask)
57a245ccebSSascha Hauer {
58a245ccebSSascha Hauer int loops = msecs_to_loops(10);
598ab432caSTony Prisk u32 mask = bitmask << (nr << 8);
608ab432caSTony Prisk
618ab432caSTony Prisk while ((readl(vt8500->base + REG_STATUS) & mask) && --loops)
62a245ccebSSascha Hauer cpu_relax();
63a245ccebSSascha Hauer
64a245ccebSSascha Hauer if (unlikely(!loops))
658ab432caSTony Prisk dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n",
668ab432caSTony Prisk mask);
67a245ccebSSascha Hauer }
68a245ccebSSascha Hauer
vt8500_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,u64 duty_ns,u64 period_ns)69a245ccebSSascha Hauer static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
7014d89565SUwe Kleine-König u64 duty_ns, u64 period_ns)
71a245ccebSSascha Hauer {
72a245ccebSSascha Hauer struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
73a245ccebSSascha Hauer unsigned long long c;
74a245ccebSSascha Hauer unsigned long period_cycles, prescale, pv, dc;
75422470a8STony Prisk int err;
768ab432caSTony Prisk u32 val;
77422470a8STony Prisk
78422470a8STony Prisk err = clk_enable(vt8500->clk);
79422470a8STony Prisk if (err < 0) {
80422470a8STony Prisk dev_err(chip->dev, "failed to enable clock\n");
81422470a8STony Prisk return err;
82422470a8STony Prisk }
83a245ccebSSascha Hauer
8463e1ed23STony Prisk c = clk_get_rate(vt8500->clk);
85a245ccebSSascha Hauer c = c * period_ns;
86a245ccebSSascha Hauer do_div(c, 1000000000);
87a245ccebSSascha Hauer period_cycles = c;
88a245ccebSSascha Hauer
89a245ccebSSascha Hauer if (period_cycles < 1)
90a245ccebSSascha Hauer period_cycles = 1;
91a245ccebSSascha Hauer prescale = (period_cycles - 1) / 4096;
92a245ccebSSascha Hauer pv = period_cycles / (prescale + 1) - 1;
93a245ccebSSascha Hauer if (pv > 4095)
94a245ccebSSascha Hauer pv = 4095;
95a245ccebSSascha Hauer
96422470a8STony Prisk if (prescale > 1023) {
97422470a8STony Prisk clk_disable(vt8500->clk);
98a245ccebSSascha Hauer return -EINVAL;
99422470a8STony Prisk }
100a245ccebSSascha Hauer
101a245ccebSSascha Hauer c = (unsigned long long)pv * duty_ns;
10214d89565SUwe Kleine-König
10314d89565SUwe Kleine-König dc = div64_u64(c, period_ns);
104a245ccebSSascha Hauer
1058ab432caSTony Prisk writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm));
106e9d866d5SUwe Kleine-König vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE);
107a245ccebSSascha Hauer
1088ab432caSTony Prisk writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm));
109e9d866d5SUwe Kleine-König vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE);
110a245ccebSSascha Hauer
1118ab432caSTony Prisk writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));
112e9d866d5SUwe Kleine-König vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE);
1138ab432caSTony Prisk
1148ab432caSTony Prisk val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
1158ab432caSTony Prisk val |= CTRL_AUTOLOAD;
1168ab432caSTony Prisk writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
117e9d866d5SUwe Kleine-König vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
118a245ccebSSascha Hauer
119422470a8STony Prisk clk_disable(vt8500->clk);
120a245ccebSSascha Hauer return 0;
121a245ccebSSascha Hauer }
122a245ccebSSascha Hauer
vt8500_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm)123a245ccebSSascha Hauer static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
124a245ccebSSascha Hauer {
125a245ccebSSascha Hauer struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
1268ab432caSTony Prisk int err;
1278ab432caSTony Prisk u32 val;
128a245ccebSSascha Hauer
12963e1ed23STony Prisk err = clk_enable(vt8500->clk);
1302f9569f7STony Prisk if (err < 0) {
13163e1ed23STony Prisk dev_err(chip->dev, "failed to enable clock\n");
13263e1ed23STony Prisk return err;
133422470a8STony Prisk }
13463e1ed23STony Prisk
1358ab432caSTony Prisk val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
1368ab432caSTony Prisk val |= CTRL_ENABLE;
1378ab432caSTony Prisk writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
138e9d866d5SUwe Kleine-König vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
1398ab432caSTony Prisk
140a245ccebSSascha Hauer return 0;
141a245ccebSSascha Hauer }
142a245ccebSSascha Hauer
vt8500_pwm_disable(struct pwm_chip * chip,struct pwm_device * pwm)143a245ccebSSascha Hauer static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
144a245ccebSSascha Hauer {
145a245ccebSSascha Hauer struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
1468ab432caSTony Prisk u32 val;
147a245ccebSSascha Hauer
1488ab432caSTony Prisk val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
1498ab432caSTony Prisk val &= ~CTRL_ENABLE;
1508ab432caSTony Prisk writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
151e9d866d5SUwe Kleine-König vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
15263e1ed23STony Prisk
15363e1ed23STony Prisk clk_disable(vt8500->clk);
154a245ccebSSascha Hauer }
155a245ccebSSascha Hauer
vt8500_pwm_set_polarity(struct pwm_chip * chip,struct pwm_device * pwm,enum pwm_polarity polarity)1563ccb1c17STony Prisk static int vt8500_pwm_set_polarity(struct pwm_chip *chip,
1573ccb1c17STony Prisk struct pwm_device *pwm,
1583ccb1c17STony Prisk enum pwm_polarity polarity)
1593ccb1c17STony Prisk {
1603ccb1c17STony Prisk struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
1613ccb1c17STony Prisk u32 val;
1623ccb1c17STony Prisk
1633ccb1c17STony Prisk val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
1643ccb1c17STony Prisk
1653ccb1c17STony Prisk if (polarity == PWM_POLARITY_INVERSED)
1663ccb1c17STony Prisk val |= CTRL_INVERT;
1673ccb1c17STony Prisk else
1683ccb1c17STony Prisk val &= ~CTRL_INVERT;
1693ccb1c17STony Prisk
1703ccb1c17STony Prisk writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
171e9d866d5SUwe Kleine-König vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
1723ccb1c17STony Prisk
1733ccb1c17STony Prisk return 0;
1743ccb1c17STony Prisk }
1753ccb1c17STony Prisk
vt8500_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)17614d89565SUwe Kleine-König static int vt8500_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
17714d89565SUwe Kleine-König const struct pwm_state *state)
17814d89565SUwe Kleine-König {
17914d89565SUwe Kleine-König int err;
18014d89565SUwe Kleine-König bool enabled = pwm->state.enabled;
18114d89565SUwe Kleine-König
18214d89565SUwe Kleine-König if (state->polarity != pwm->state.polarity) {
18314d89565SUwe Kleine-König /*
18414d89565SUwe Kleine-König * Changing the polarity of a running PWM is only allowed when
18514d89565SUwe Kleine-König * the PWM driver implements ->apply().
18614d89565SUwe Kleine-König */
18714d89565SUwe Kleine-König if (enabled) {
18814d89565SUwe Kleine-König vt8500_pwm_disable(chip, pwm);
18914d89565SUwe Kleine-König
19014d89565SUwe Kleine-König enabled = false;
19114d89565SUwe Kleine-König }
19214d89565SUwe Kleine-König
19314d89565SUwe Kleine-König err = vt8500_pwm_set_polarity(chip, pwm, state->polarity);
19414d89565SUwe Kleine-König if (err)
19514d89565SUwe Kleine-König return err;
19614d89565SUwe Kleine-König }
19714d89565SUwe Kleine-König
19814d89565SUwe Kleine-König if (!state->enabled) {
19914d89565SUwe Kleine-König if (enabled)
20014d89565SUwe Kleine-König vt8500_pwm_disable(chip, pwm);
20114d89565SUwe Kleine-König
20214d89565SUwe Kleine-König return 0;
20314d89565SUwe Kleine-König }
20414d89565SUwe Kleine-König
20514d89565SUwe Kleine-König /*
20614d89565SUwe Kleine-König * We cannot skip calling ->config even if state->period ==
20714d89565SUwe Kleine-König * pwm->state.period && state->duty_cycle == pwm->state.duty_cycle
20814d89565SUwe Kleine-König * because we might have exited early in the last call to
209a10c3d5fSSean Young * pwm_apply_might_sleep because of !state->enabled and so the two values in
21014d89565SUwe Kleine-König * pwm->state might not be configured in hardware.
21114d89565SUwe Kleine-König */
21214d89565SUwe Kleine-König err = vt8500_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
21314d89565SUwe Kleine-König if (err)
21414d89565SUwe Kleine-König return err;
21514d89565SUwe Kleine-König
21614d89565SUwe Kleine-König if (!enabled)
21714d89565SUwe Kleine-König err = vt8500_pwm_enable(chip, pwm);
21814d89565SUwe Kleine-König
21914d89565SUwe Kleine-König return err;
22014d89565SUwe Kleine-König }
22114d89565SUwe Kleine-König
222b2ec9efcSBhumika Goyal static const struct pwm_ops vt8500_pwm_ops = {
22314d89565SUwe Kleine-König .apply = vt8500_pwm_apply,
224a245ccebSSascha Hauer .owner = THIS_MODULE,
225a245ccebSSascha Hauer };
226a245ccebSSascha Hauer
22763e1ed23STony Prisk static const struct of_device_id vt8500_pwm_dt_ids[] = {
22863e1ed23STony Prisk { .compatible = "via,vt8500-pwm", },
22963e1ed23STony Prisk { /* Sentinel */ }
23063e1ed23STony Prisk };
23163e1ed23STony Prisk MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids);
23263e1ed23STony Prisk
vt8500_pwm_probe(struct platform_device * pdev)23363e1ed23STony Prisk static int vt8500_pwm_probe(struct platform_device *pdev)
234a245ccebSSascha Hauer {
235635d324eSzhaoxiao struct vt8500_chip *vt8500;
23663e1ed23STony Prisk struct device_node *np = pdev->dev.of_node;
237a245ccebSSascha Hauer int ret;
238a245ccebSSascha Hauer
23963e1ed23STony Prisk if (!np) {
24063e1ed23STony Prisk dev_err(&pdev->dev, "invalid devicetree node\n");
24163e1ed23STony Prisk return -EINVAL;
24263e1ed23STony Prisk }
24363e1ed23STony Prisk
244635d324eSzhaoxiao vt8500 = devm_kzalloc(&pdev->dev, sizeof(*vt8500), GFP_KERNEL);
245635d324eSzhaoxiao if (vt8500 == NULL)
246a245ccebSSascha Hauer return -ENOMEM;
247a245ccebSSascha Hauer
248635d324eSzhaoxiao vt8500->chip.dev = &pdev->dev;
249635d324eSzhaoxiao vt8500->chip.ops = &vt8500_pwm_ops;
250635d324eSzhaoxiao vt8500->chip.npwm = VT8500_NR_PWMS;
251a245ccebSSascha Hauer
252635d324eSzhaoxiao vt8500->clk = devm_clk_get(&pdev->dev, NULL);
253635d324eSzhaoxiao if (IS_ERR(vt8500->clk)) {
25463e1ed23STony Prisk dev_err(&pdev->dev, "clock source not specified\n");
255635d324eSzhaoxiao return PTR_ERR(vt8500->clk);
25663e1ed23STony Prisk }
25763e1ed23STony Prisk
258635d324eSzhaoxiao vt8500->base = devm_platform_ioremap_resource(pdev, 0);
259635d324eSzhaoxiao if (IS_ERR(vt8500->base))
260635d324eSzhaoxiao return PTR_ERR(vt8500->base);
261a245ccebSSascha Hauer
262635d324eSzhaoxiao ret = clk_prepare(vt8500->clk);
26363e1ed23STony Prisk if (ret < 0) {
26463e1ed23STony Prisk dev_err(&pdev->dev, "failed to prepare clock\n");
265a245ccebSSascha Hauer return ret;
26663e1ed23STony Prisk }
26763e1ed23STony Prisk
268635d324eSzhaoxiao ret = pwmchip_add(&vt8500->chip);
26963e1ed23STony Prisk if (ret < 0) {
27063e1ed23STony Prisk dev_err(&pdev->dev, "failed to add PWM chip\n");
271635d324eSzhaoxiao clk_unprepare(vt8500->clk);
27263e1ed23STony Prisk return ret;
27363e1ed23STony Prisk }
274a245ccebSSascha Hauer
275635d324eSzhaoxiao platform_set_drvdata(pdev, vt8500);
276a245ccebSSascha Hauer return ret;
277a245ccebSSascha Hauer }
278a245ccebSSascha Hauer
vt8500_pwm_remove(struct platform_device * pdev)27922e1d1f4SUwe Kleine-König static void vt8500_pwm_remove(struct platform_device *pdev)
280a245ccebSSascha Hauer {
281635d324eSzhaoxiao struct vt8500_chip *vt8500 = platform_get_drvdata(pdev);
282a245ccebSSascha Hauer
283635d324eSzhaoxiao pwmchip_remove(&vt8500->chip);
284a245ccebSSascha Hauer
285635d324eSzhaoxiao clk_unprepare(vt8500->clk);
286a245ccebSSascha Hauer }
287a245ccebSSascha Hauer
28863e1ed23STony Prisk static struct platform_driver vt8500_pwm_driver = {
28963e1ed23STony Prisk .probe = vt8500_pwm_probe,
29022e1d1f4SUwe Kleine-König .remove_new = vt8500_pwm_remove,
291a245ccebSSascha Hauer .driver = {
292a245ccebSSascha Hauer .name = "vt8500-pwm",
29363e1ed23STony Prisk .of_match_table = vt8500_pwm_dt_ids,
294a245ccebSSascha Hauer },
295a245ccebSSascha Hauer };
29663e1ed23STony Prisk module_platform_driver(vt8500_pwm_driver);
297a245ccebSSascha Hauer
29863e1ed23STony Prisk MODULE_DESCRIPTION("VT8500 PWM Driver");
29963e1ed23STony Prisk MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
30063e1ed23STony Prisk MODULE_LICENSE("GPL v2");
301