Lines Matching +full:pwm +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PWM Controller Driver for HiSilicon BVT SoCs
15 #include <linux/pwm.h>
18 #define PWM_CFG0_ADDR(x) (((x) * 0x20) + 0x0)
19 #define PWM_CFG1_ADDR(x) (((x) * 0x20) + 0x4)
20 #define PWM_CFG2_ADDR(x) (((x) * 0x20) + 0x8)
21 #define PWM_CTRL_ADDR(x) (((x) * 0x20) + 0xC)
23 #define PWM_ENABLE_SHIFT 0
24 #define PWM_ENABLE_MASK BIT(0)
32 #define PWM_PERIOD_MASK GENMASK(31, 0)
33 #define PWM_DUTY_MASK GENMASK(31, 0)
83 static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in hibvt_pwm_enable() argument
87 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
88 PWM_ENABLE_MASK, 0x1); in hibvt_pwm_enable()
91 static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) in hibvt_pwm_disable() argument
95 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
96 PWM_ENABLE_MASK, 0x0); in hibvt_pwm_disable()
99 static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in hibvt_pwm_config() argument
105 freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000); in hibvt_pwm_config()
110 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm), in hibvt_pwm_config()
113 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm), in hibvt_pwm_config()
118 struct pwm_device *pwm, in hibvt_pwm_set_polarity() argument
124 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
125 PWM_POLARITY_MASK, (0x1 << PWM_POLARITY_SHIFT)); in hibvt_pwm_set_polarity()
127 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
128 PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT)); in hibvt_pwm_set_polarity()
131 static int hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in hibvt_pwm_get_state() argument
138 freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000); in hibvt_pwm_get_state()
139 base = hi_pwm_chip->base; in hibvt_pwm_get_state()
141 value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
142 state->period = div_u64(value * 1000, freq); in hibvt_pwm_get_state()
144 value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
145 state->duty_cycle = div_u64(value * 1000, freq); in hibvt_pwm_get_state()
147 value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
148 state->enabled = (PWM_ENABLE_MASK & value); in hibvt_pwm_get_state()
149 state->polarity = (PWM_POLARITY_MASK & value) ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; in hibvt_pwm_get_state()
151 return 0; in hibvt_pwm_get_state()
154 static int hibvt_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in hibvt_pwm_apply() argument
159 if (state->polarity != pwm->state.polarity) in hibvt_pwm_apply()
160 hibvt_pwm_set_polarity(chip, pwm, state->polarity); in hibvt_pwm_apply()
162 if (state->period != pwm->state.period || in hibvt_pwm_apply()
163 state->duty_cycle != pwm->state.duty_cycle) { in hibvt_pwm_apply()
164 hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period); in hibvt_pwm_apply()
167 * Some implementations require the PWM to be enabled twice in hibvt_pwm_apply()
170 if (hi_pwm_chip->soc->quirk_force_enable && state->enabled) in hibvt_pwm_apply()
171 hibvt_pwm_enable(chip, pwm); in hibvt_pwm_apply()
174 if (state->enabled != pwm->state.enabled) { in hibvt_pwm_apply()
175 if (state->enabled) in hibvt_pwm_apply()
176 hibvt_pwm_enable(chip, pwm); in hibvt_pwm_apply()
178 hibvt_pwm_disable(chip, pwm); in hibvt_pwm_apply()
181 return 0; in hibvt_pwm_apply()
194 of_device_get_match_data(&pdev->dev); in hibvt_pwm_probe()
198 pwm_chip = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip), GFP_KERNEL); in hibvt_pwm_probe()
200 return -ENOMEM; in hibvt_pwm_probe()
202 pwm_chip->clk = devm_clk_get(&pdev->dev, NULL); in hibvt_pwm_probe()
203 if (IS_ERR(pwm_chip->clk)) { in hibvt_pwm_probe()
204 dev_err(&pdev->dev, "getting clock failed with %ld\n", in hibvt_pwm_probe()
205 PTR_ERR(pwm_chip->clk)); in hibvt_pwm_probe()
206 return PTR_ERR(pwm_chip->clk); in hibvt_pwm_probe()
209 pwm_chip->chip.ops = &hibvt_pwm_ops; in hibvt_pwm_probe()
210 pwm_chip->chip.dev = &pdev->dev; in hibvt_pwm_probe()
211 pwm_chip->chip.npwm = soc->num_pwms; in hibvt_pwm_probe()
212 pwm_chip->soc = soc; in hibvt_pwm_probe()
214 pwm_chip->base = devm_platform_ioremap_resource(pdev, 0); in hibvt_pwm_probe()
215 if (IS_ERR(pwm_chip->base)) in hibvt_pwm_probe()
216 return PTR_ERR(pwm_chip->base); in hibvt_pwm_probe()
218 ret = clk_prepare_enable(pwm_chip->clk); in hibvt_pwm_probe()
219 if (ret < 0) in hibvt_pwm_probe()
222 pwm_chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); in hibvt_pwm_probe()
223 if (IS_ERR(pwm_chip->rstc)) { in hibvt_pwm_probe()
224 clk_disable_unprepare(pwm_chip->clk); in hibvt_pwm_probe()
225 return PTR_ERR(pwm_chip->rstc); in hibvt_pwm_probe()
228 reset_control_assert(pwm_chip->rstc); in hibvt_pwm_probe()
230 reset_control_deassert(pwm_chip->rstc); in hibvt_pwm_probe()
232 ret = pwmchip_add(&pwm_chip->chip); in hibvt_pwm_probe()
233 if (ret < 0) { in hibvt_pwm_probe()
234 clk_disable_unprepare(pwm_chip->clk); in hibvt_pwm_probe()
238 for (i = 0; i < pwm_chip->chip.npwm; i++) { in hibvt_pwm_probe()
239 hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i), in hibvt_pwm_probe()
240 PWM_KEEP_MASK, (0x1 << PWM_KEEP_SHIFT)); in hibvt_pwm_probe()
245 return 0; in hibvt_pwm_probe()
254 pwmchip_remove(&pwm_chip->chip); in hibvt_pwm_remove()
256 reset_control_assert(pwm_chip->rstc); in hibvt_pwm_remove()
258 reset_control_deassert(pwm_chip->rstc); in hibvt_pwm_remove()
260 clk_disable_unprepare(pwm_chip->clk); in hibvt_pwm_remove()
264 { .compatible = "hisilicon,hi3516cv300-pwm",
266 { .compatible = "hisilicon,hi3519v100-pwm",
268 { .compatible = "hisilicon,hi3559v100-shub-pwm",
270 { .compatible = "hisilicon,hi3559v100-pwm",
278 .name = "hibvt-pwm",
287 MODULE_DESCRIPTION("HiSilicon BVT SoCs PWM driver");