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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.core_prefetch1 Core instruction prefetch disable
3 To disable instruction prefetch of core; hwconfig needs to be updated.
13 If the bit is set ('b1) in the mask, then prefetch is disabled for
16 core0 prefetch should not be disabled i.e. Mask[0] should never be set.
19 Once disabled, prefetch remains disabled until the next reset.
20 There is no function to re-enable prefetch.
/openbmc/u-boot/arch/mips/mach-pic32/
H A Dcpu.c14 /* Flash prefetch */
55 /* initialize prefetch module related to cpu_clk */
89 /* Enable prefetch for all */ in prefetch_init()
97 /* flash prefetch */ in arch_cpu_init_dm()
/openbmc/qemu/qapi/
H A Dpci.json42 # @prefetch: if @type is 'memory', true if the memory is prefetchable
50 '*prefetch': 'bool', '*mem_type_64': 'bool' } }
263 # "prefetch": true,
271 # "prefetch": false,
279 # "prefetch": false,
/openbmc/qemu/target/hexagon/imported/
H A Dsystem.idef43 …tch(Rs32+#u11:3)",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH),"Data Cache Prefetch",{fEA_RI(RsV,uiV)…
52 Q6INSN(Y4_l2fetch,"l2fetch(Rs32,Rt32)",ATTRIBS(A_RESTRICT_SLOT0ONLY),"L2 Cache Prefetch",
62 Q6INSN(Y5_l2fetch,"l2fetch(Rs32,Rtt32)",ATTRIBS(A_RESTRICT_SLOT0ONLY),"L2 Cache Prefetch",
/openbmc/u-boot/include/linux/
H A Dlist.h9 static inline void prefetch(const void *x) {;} in prefetch() function
357 for (pos = (head)->next; prefetch(pos->next), pos != (head); \
379 for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \
400 prefetch(pos->prev), pos != (head); \
411 prefetch(pos->member.next), &pos->member != (head); \
422 prefetch(pos->member.prev), &pos->member != (head); \
447 prefetch(pos->member.next), &pos->member != (head); \
461 prefetch(pos->member.prev), &pos->member != (head); \
473 for (; prefetch(pos->member.next), &pos->member != (head); \
628 for (pos = (head)->first; pos && ({ prefetch(pos->next); 1; }); \
[all …]
/openbmc/qemu/docs/devel/
H A Ds390-dasd-ipl.rst77 non-prefetch of ccw data.
80 ORB (Operation Request Block). One of those parameters is a prefetch bit. If the
90 Not being able to turn off prefetch will also prevent the TIC at the end of the
100 Since we are forced to live with prefetch we cannot use the very simple IPL
/openbmc/u-boot/board/freescale/mpc837xerdb/
H A DREADME41 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 32
42 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 32
/openbmc/u-boot/board/freescale/mpc837xemds/
H A DREADME45 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
46 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
/openbmc/u-boot/drivers/pci/
H A Dpci_auto.c22 struct pci_region *prefetch, struct pci_region *io, in dm_pciauto_setup_device() argument
87 if (prefetch && (bar_response & in dm_pciauto_setup_device()
89 bar_res = prefetch; in dm_pciauto_setup_device()
96 bar_nr, bar_res == prefetch ? "Prf" : "Mem", in dm_pciauto_setup_device()
H A Dpci_auto_old.c31 struct pci_region *prefetch, in pciauto_setup_device() argument
99 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH)) in pciauto_setup_device()
100 bar_res = prefetch; in pciauto_setup_device()
105 bar_nr, bar_res == prefetch ? "Prf" : "Mem", in pciauto_setup_device()
/openbmc/u-boot/drivers/usb/gadget/
H A Dpxa25x_udc.h21 static inline void prefetch(const void *ptr) in prefetch() function
30 #define prefetchw(ptr) prefetch(ptr)
/openbmc/u-boot/board/freescale/mpc832xemds/
H A DREADME66 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
67 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
/openbmc/u-boot/arch/arm/mach-imx/
H A Dcache.c115 /* Turn on the L2 I/D prefetch, double linefill */ in v7_outer_cache_enable()
116 /* Set prefetch offset with any value except 23 as per errata 765569 */ in v7_outer_cache_enable()
/openbmc/libcper/include/libcper/sections/
H A Dcper-section-arm.h56 "Prefetch", "Eviction", "Snooping", \
66 "Prefetch", \
H A Dcper-section-ia32x64.h40 "Prefetch", "Eviction", "Snoop" }
/openbmc/u-boot/arch/powerpc/lib/
H A Dcache.c33 /* flush prefetch queue */ in flush_cache()
/openbmc/u-boot/doc/
H A DREADME.NDS3222 - Data prefetch to improve data cache performance.
/openbmc/u-boot/arch/mips/mach-pic32/include/mach/
H A Dpic32.h44 /* Prefetch Module */
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-benchmark/tinymembench/
H A Dtinymembench_git.bb4 aligned memory blocks and attempting different prefetch strategies"
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_cache.S18 test prefetch
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Drelocate.S26 * 0x0000000c prefetch abort indirect branch to [0xfffffef8]
/openbmc/u-boot/cmd/
H A Dpci.c214 { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
215 { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
216 { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
217 { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
615 { PCI_REGION_PREFETCH, "prefetch" },
/openbmc/u-boot/drivers/mtd/nand/raw/
H A DKconfig106 bool "Enable GPMC Prefetch"
112 uses the prefetch mode to speed up read operations.
/openbmc/qemu/tests/tcg/arm/system/
H A Dboot.S36 b prefetch_abort /* prefetch abort vector */
287 .ascii "Prefetch Abort Occurred.\n\0"
/openbmc/qemu/tests/qemu-iotests/tests/
H A Dstream-unaligned-prefetch4 # Test what happens when a stream job does an unaligned prefetch read

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