1*83d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0+ */ 2db544b96SAlbert ARIBAUD/* 3db544b96SAlbert ARIBAUD * relocate - i.MX27-specific vector relocation 4db544b96SAlbert ARIBAUD * 5db544b96SAlbert ARIBAUD * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net> 6db544b96SAlbert ARIBAUD */ 7db544b96SAlbert ARIBAUD 8db544b96SAlbert ARIBAUD#include <asm-offsets.h> 9db544b96SAlbert ARIBAUD#include <config.h> 10db544b96SAlbert ARIBAUD#include <linux/linkage.h> 11db544b96SAlbert ARIBAUD 12db544b96SAlbert ARIBAUD/* 13db544b96SAlbert ARIBAUD * The i.MX27 SoC is very specific with respect to exceptions: it 14db544b96SAlbert ARIBAUD * does not provide RAM at the high vectors address (0xFFFF0000), 15db544b96SAlbert ARIBAUD * thus only the low address (0x00000000) is useable; but that is 16db544b96SAlbert ARIBAUD * in ROM. Therefore, vectors cannot be changed at all. 17db544b96SAlbert ARIBAUD * 18db544b96SAlbert ARIBAUD * However, these ROM-based vectors actually just perform indirect 19db544b96SAlbert ARIBAUD * calls through pointers located in RAM at SoC-specific addresses, 20db544b96SAlbert ARIBAUD * as follows: 21db544b96SAlbert ARIBAUD * 22db544b96SAlbert ARIBAUD * Offset Exception Use by ROM code 23db544b96SAlbert ARIBAUD * 0x00000000 reset indirect branch to [0x00000014] 24db544b96SAlbert ARIBAUD * 0x00000004 undefined instruction indirect branch to [0xfffffef0] 25db544b96SAlbert ARIBAUD * 0x00000008 software interrupt indirect branch to [0xfffffef4] 26db544b96SAlbert ARIBAUD * 0x0000000c prefetch abort indirect branch to [0xfffffef8] 27db544b96SAlbert ARIBAUD * 0x00000010 data abort indirect branch to [0xfffffefc] 28db544b96SAlbert ARIBAUD * 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000 29db544b96SAlbert ARIBAUD * 0x00000018 IRQ indirect branch to [0xffffff00] 30db544b96SAlbert ARIBAUD * 0x0000001c FIQ indirect branch to [0xffffff04] 31db544b96SAlbert ARIBAUD * 32db544b96SAlbert ARIBAUD * In order to initialize exceptions on i.MX27, we must copy U-Boot's 33db544b96SAlbert ARIBAUD * indirect (not exception!) vector table into 0xfffffef0..0xffffff04 34db544b96SAlbert ARIBAUD * taking care not to copy vectors number 5 (reserved exception). 35db544b96SAlbert ARIBAUD */ 36db544b96SAlbert ARIBAUD 37db544b96SAlbert ARIBAUD .section .text.relocate_vectors,"ax",%progbits 38db544b96SAlbert ARIBAUD 39db544b96SAlbert ARIBAUDENTRY(relocate_vectors) 40db544b96SAlbert ARIBAUD 41db544b96SAlbert ARIBAUD ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ 42db544b96SAlbert ARIBAUD ldr r1, =32 /* size of vector table */ 43db544b96SAlbert ARIBAUD add r0, r0, r1 /* skip to indirect table */ 44db544b96SAlbert ARIBAUD ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */ 45db544b96SAlbert ARIBAUD ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */ 46db544b96SAlbert ARIBAUD stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */ 47db544b96SAlbert ARIBAUD 48db544b96SAlbert ARIBAUD bx lr 49db544b96SAlbert ARIBAUD 50db544b96SAlbert ARIBAUDENDPROC(relocate_vectors) 51