| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | ti,gpmc-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
20 - enum:
21 - ti,am64-nand
22 - ti,omap2-nand
29 - description: Interrupt for fifoevent
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| /openbmc/linux/tools/perf/pmu-events/arch/nds32/n13/ |
| H A D | atcpmu.json | 15 "PublicDescription": "Prefetch Instruction",
18 "BriefDescription": "V3 Prefetch Instruction"
27 "PublicDescription": "JR(non-RET) instructions",
30 "BriefDescription": "V3 JR(non-RET) instructions"
123 "PublicDescription": "DMA BIU CYCLES",
126 "BriefDescription": "V3 DMA BIU CYCLES"
165 "PublicDescription": "Prefetch Instructions with cache hit",
168 "BriefDescription": "V3 Prefetch Instructions with cache hit"
201 "PublicDescription": "ld-after-st conflict replays",
204 "BriefDescription": "V3 ld-after-st conflict replays"
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| /openbmc/linux/drivers/net/wireless/mediatek/mt76/ |
| H A D | mt792x_dma.c | 1 // SPDX-License-Identifier: ISC
8 #include "dma.h"
15 if (test_bit(MT76_REMOVED, &dev->mt76.phy.state)) in mt792x_irq_handler()
17 mt76_wr(dev, dev->irq_map->host_irq_enable, 0); in mt792x_irq_handler()
19 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) in mt792x_irq_handler()
22 tasklet_schedule(&dev->mt76.irq_tasklet); in mt792x_irq_handler()
31 const struct mt792x_irq_map *irq_map = dev->irq_map; in mt792x_irq_tasklet()
34 mt76_wr(dev, irq_map->host_irq_enable, 0); in mt792x_irq_tasklet()
37 intr &= dev->mt76.mmio.irqmask; in mt792x_irq_tasklet()
40 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt792x_irq_tasklet()
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| /openbmc/linux/drivers/net/ethernet/sfc/ |
| H A D | tx_tso.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2015 Solarflare Communications Inc.
34 #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
37 * struct tso_state - TSO state for an SKB
42 * @dma_addr: DMA address of current position
45 * @unmap_addr: DMA address of SKB fragment
51 * @header_dma_addr: Header DMA address
52 * @header_unmap_len: Header DMA mapped length
84 ptr = (char *) (tx_queue->buffer + insert_ptr); in prefetch_ptr()
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| /openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7996/ |
| H A D | dma.c | 1 // SPDX-License-Identifier: ISC
7 #include "../dma.h"
16 mt76_connac_tx_cleanup(&dev->mt76); in mt7996_poll_tx()
27 dev->q_wfdma_mask |= (1 << (q)); \ in mt7996_dma_config()
28 dev->q_int_mask[(q)] = int; \ in mt7996_dma_config()
29 dev->q_id[(q)] = id; \ in mt7996_dma_config()
61 #define PREFETCH(_base, _depth) ((_base) << 16 | (_depth)) in __mt7996_dma_prefetch() macro
62 /* prefetch SRAM wrapping boundary for tx/rx ring. */ in __mt7996_dma_prefetch()
63 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x2)); in __mt7996_dma_prefetch()
64 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x20, 0x2)); in __mt7996_dma_prefetch()
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| /openbmc/linux/arch/arm/boot/dts/axis/ |
| H A D | artpec6.dtsi | 2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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| /openbmc/linux/drivers/comedi/drivers/ |
| H A D | plx9080.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
34 * will be transferred by the DMA engine from local or PCI memory into
35 * corresponding registers for the DMA channel.
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
82 /* DMA Arbitration Register (alias of MARBR). */
99 /* DMA Channel Priority */
101 #define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | omap2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-ecc-sw-bch.h>
21 #include <linux/omap-dma.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
156 struct dma_chan *dma; member
198 * omap_prefetch_enable - configures and starts prefetch transfer
201 * @dma_mode: dma mode enable (1) or disable (0)
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| /openbmc/linux/drivers/net/ethernet/intel/igbvf/ |
| H A D | igbvf.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009 - 2018 Intel Corporation. */
52 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
54 * Setting this to 0 disables RX descriptor prefetch.
55 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
58 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
79 #define IGBVF_MNG_VLAN_NONE (-1)
84 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
97 * so a DMA handle can be stored along with the buffer
100 dma_addr_t dma; member
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | ti,gpmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
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| /openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7915/ |
| H A D | dma.c | 1 // SPDX-License-Identifier: ISC
5 #include "../dma.h"
11 struct mt7915_dev *dev = phy->dev; in mt7915_init_tx_queues()
13 if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) { in mt7915_init_tx_queues()
14 if (is_mt798x(&dev->mt76)) in mt7915_init_tx_queues()
19 idx -= MT_TXQ_ID(0); in mt7915_init_tx_queues()
22 return mt76_connac_init_tx_queues(phy->mt76, idx, n_desc, ring_base, in mt7915_init_tx_queues()
32 mt76_connac_tx_cleanup(&dev->mt76); in mt7915_poll_tx()
43 dev->wfdma_mask |= (1 << (q)); \ in mt7915_dma_config()
44 dev->q_int_mask[(q)] = int; \ in mt7915_dma_config()
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| /openbmc/linux/Documentation/devicetree/bindings/cache/ |
| H A D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
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| /openbmc/linux/arch/arm/mm/ |
| H A D | cache-fa.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-fa.S
6 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
8 * Based on cache-v4wb.S:
9 * Copyright (C) 1997-2002 Russell king
18 #include "proc-macros.S"
70 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
79 * - start - start address (inclusive, page aligned)
80 * - end - end address (exclusive, page aligned)
81 * - flags - vma_area_struct flags describing address space
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| H A D | proc-xsc3.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-xsc3.S
15 * - ARMv6 Supersections
16 * - Low Locality Reference pages (replaces mini-cache)
17 * - 36-bit addressing
18 * - L2 cache
19 * - Cache coherency if chipset supports it
29 #include <asm/pgtable-hwdef.h>
32 #include "proc-macros.S"
175 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
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| /openbmc/linux/arch/arc/mm/ |
| H A D | dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 #include <linux/dma-map-ops.h>
11 * ARCH specific callbacks for generic noncoherent DMA ops
12 * - hardware IOC not available (or "dma-coherent" not set for device in DT)
13 * - But still handle both coherent and non-coherent requests from caller
15 * For DMA coherent hardware (IOC) generic code suffices
23 * Yeah this bit us - STAR 9000898266 in arch_dma_prep_coherent()
37 * dma-mapping: provide a generic dma-noncoherent implementation)"
40 * |----------------------------------------------------------------
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| /openbmc/linux/drivers/net/ethernet/pasemi/ |
| H A D | pasemi_mac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
17 #include <asm/dma-mapping.h>
23 #include <linux/prefetch.h>
34 * unaligned DMA, so make sure the data is aligned instead.
40 * - Multicast support
41 * - Large MTU support
42 * - Multiqueue RX/TX
63 static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
85 return pasemi_read_mac_reg(mac->dma_if, reg); in read_mac_reg()
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| /openbmc/linux/drivers/net/ethernet/intel/ixgbe/ |
| H A D | ixgbe_xsk.c | 1 // SPDX-License-Identifier: GPL-2.0
14 bool xdp_on = READ_ONCE(adapter->xdp_prog); in ixgbe_xsk_pool()
15 int qid = ring->ring_idx; in ixgbe_xsk_pool()
17 if (!xdp_on || !test_bit(qid, adapter->af_xdp_zc_qps)) in ixgbe_xsk_pool()
20 return xsk_get_pool_from_qid(adapter->netdev, qid); in ixgbe_xsk_pool()
27 struct net_device *netdev = adapter->netdev; in ixgbe_xsk_pool_enable()
31 if (qid >= adapter->num_rx_queues) in ixgbe_xsk_pool_enable()
32 return -EINVAL; in ixgbe_xsk_pool_enable()
34 if (qid >= netdev->real_num_rx_queues || in ixgbe_xsk_pool_enable()
35 qid >= netdev->real_num_tx_queues) in ixgbe_xsk_pool_enable()
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| /openbmc/linux/drivers/gpu/drm/etnaviv/ |
| H A D | etnaviv_iommu_v2.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Etnaviv Project
7 #include <linux/dma-mapping.h>
52 drm_mm_takedown(&context->mm); in etnaviv_iommuv2_free()
55 if (v2_context->stlb_cpu[i]) in etnaviv_iommuv2_free()
56 dma_free_wc(context->global->dev, SZ_4K, in etnaviv_iommuv2_free()
57 v2_context->stlb_cpu[i], in etnaviv_iommuv2_free()
58 v2_context->stlb_dma[i]); in etnaviv_iommuv2_free()
61 dma_free_wc(context->global->dev, SZ_4K, v2_context->mtlb_cpu, in etnaviv_iommuv2_free()
62 v2_context->mtlb_dma); in etnaviv_iommuv2_free()
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| /openbmc/linux/arch/riscv/mm/ |
| H A D | dma-noncoherent.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V specific functions to support DMA for non-coherent devices
8 #include <linux/dma-direct.h>
9 #include <linux/dma-map-ops.h>
12 #include <asm/dma-noncoherent.h>
107 /* FROM_DEVICE invalidate needed if speculative CPU prefetch only */ in arch_sync_dma_for_cpu()
136 "%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)", in arch_setup_dma_ops()
141 "%s %s: device non-coherent but no non-coherent operations supported", in arch_setup_dma_ops()
144 dev->dma_coherent = coherent; in arch_setup_dma_ops()
150 "Non-coherent DMA support enabled without a block size\n"); in riscv_noncoherent_supported()
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | recommended.json | 4 "BriefDescription": "Execution-time branch misprediction ratio (non-speculative).",
23 "BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch).",
29 "BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch).",
216 "BriefDescription": "Macro-ops dispatched.",
227 "BriefDescription": "Macro-ops retired.",
236 "ScaleUnit": "6.103515625e-5MiB"
244 "ScaleUnit": "6.103515625e-5MiB"
252 "ScaleUnit": "6.103515625e-5MiB"
260 "ScaleUnit": "6.103515625e-5MiB"
264 "BriefDescription": "Local socket upstream DMA read data.",
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| /openbmc/linux/drivers/net/ethernet/huawei/hinic/ |
| H A D | hinic_rx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/dma-mapping.h>
19 #include <linux/prefetch.h>
46 (HINIC_GET_RX_PKT_TYPE(be32_to_cpu((cqe)->offload_type)) == \
50 * hinic_rxq_clean_stats - Clean the statistics of specific queue
55 struct hinic_rxq_stats *rxq_stats = &rxq->rxq_stats; in hinic_rxq_clean_stats()
57 u64_stats_update_begin(&rxq_stats->syncp); in hinic_rxq_clean_stats()
58 rxq_stats->pkts = 0; in hinic_rxq_clean_stats()
59 rxq_stats->bytes = 0; in hinic_rxq_clean_stats()
60 rxq_stats->errors = 0; in hinic_rxq_clean_stats()
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| /openbmc/linux/drivers/block/mtip32xx/ |
| H A D | mtip32xx.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * mtip32xx.h - Header file for the P320 SSD Block Driver
67 * NOTE: This is the driver maximum; check dd->slot_groups for actual value.
95 * Per-tag bitfield size in longs.
104 (U32_PER_LONG-1))/U32_PER_LONG)
181 mtip_workq_sdbfx(w->port, group, w->completed); \
188 * - 27h Register FIS, host to device.
189 * - 34h Register FIS, device to host.
190 * - 39h DMA Activate FIS, device to host.
191 * - 41h DMA Setup FIS, bi-directional.
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| /openbmc/linux/Documentation/devicetree/bindings/iommu/ |
| H A D | arm,smmu-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
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| /openbmc/linux/drivers/parisc/ |
| H A D | iommu-helpers.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <linux/prefetch.h>
5 * iommu_fill_pdir - Insert coalesced scatter/gather chunks into the I/O Pdir.
9 * @hint: The DMA Hint.
20 struct scatterlist *dma_sg = startsg; /* pointer to current DMA */ in iommu_fill_pdir()
28 dma_sg--; in iommu_fill_pdir()
30 while (nents-- > 0) { in iommu_fill_pdir()
36 sg_virt(startsg), startsg->length in iommu_fill_pdir()
41 ** Look for the start of a new DMA stream in iommu_fill_pdir()
57 sg_dma_address(dma_sg) = pide | ioc->ibase; in iommu_fill_pdir()
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| /openbmc/u-boot/drivers/usb/gadget/ |
| H A D | pxa25x_udc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Intel PXA25x on-chip full speed USB device controller
14 #include <asm/arch/regs-usb.h>
17 * Prefetching support - only ARMv5.
21 static inline void prefetch(const void *ptr) in prefetch() function
30 #define prefetchw(ptr) prefetch(ptr)
33 /*-------------------------------------------------------------------------*/
37 /*-------------------------------------------------------------------------*/
65 * DRCM = DMA Request Channel Map
139 /*-------------------------------------------------------------------------*/
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