Lines Matching +full:prefetch +full:- +full:dma
1 // SPDX-License-Identifier: ISC
7 #include "../dma.h"
16 mt76_connac_tx_cleanup(&dev->mt76); in mt7996_poll_tx()
27 dev->q_wfdma_mask |= (1 << (q)); \ in mt7996_dma_config()
28 dev->q_int_mask[(q)] = int; \ in mt7996_dma_config()
29 dev->q_id[(q)] = id; \ in mt7996_dma_config()
61 #define PREFETCH(_base, _depth) ((_base) << 16 | (_depth)) in __mt7996_dma_prefetch() macro
62 /* prefetch SRAM wrapping boundary for tx/rx ring. */ in __mt7996_dma_prefetch()
63 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x2)); in __mt7996_dma_prefetch()
64 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x20, 0x2)); in __mt7996_dma_prefetch()
65 mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x40, 0x4)); in __mt7996_dma_prefetch()
66 mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0x80, 0x4)); in __mt7996_dma_prefetch()
67 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0xc0, 0x2)); in __mt7996_dma_prefetch()
68 mt76_wr(dev, MT_TXQ_EXT_CTRL(2) + ofs, PREFETCH(0xe0, 0x4)); in __mt7996_dma_prefetch()
69 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x120, 0x2)); in __mt7996_dma_prefetch()
70 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x140, 0x2)); in __mt7996_dma_prefetch()
71 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x160, 0x2)); in __mt7996_dma_prefetch()
72 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2_WA) + ofs, PREFETCH(0x180, 0x2)); in __mt7996_dma_prefetch()
73 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x1a0, 0x10)); in __mt7996_dma_prefetch()
74 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2) + ofs, PREFETCH(0x2a0, 0x10)); in __mt7996_dma_prefetch()
82 if (dev->hif2) in mt7996_dma_prefetch()
83 __mt7996_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0)); in mt7996_dma_prefetch()
90 if (dev->hif2) in mt7996_dma_disable()
91 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7996_dma_disable()
102 if (dev->hif2) { in mt7996_dma_disable()
121 if (dev->hif2) { in mt7996_dma_disable()
136 if (dev->hif2) in mt7996_dma_start()
137 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7996_dma_start()
147 if (dev->hif2) in mt7996_dma_start()
162 if (!dev->mphy.band_idx) in mt7996_dma_start()
165 if (dev->dbdc_support) in mt7996_dma_start()
168 if (dev->tbtc_support) in mt7996_dma_start()
180 if (dev->hif2) in mt7996_dma_enable()
181 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7996_dma_enable()
183 /* reset dma idx */ in mt7996_dma_enable()
185 if (dev->hif2) in mt7996_dma_enable()
193 if (dev->hif2) { in mt7996_dma_enable()
208 if (dev->hif2) in mt7996_dma_enable()
226 if (dev->hif2) { in mt7996_dma_enable()
240 if (dev->hif2) { in mt7996_dma_enable()
260 mt76_dma_attach(&dev->mt76); in mt7996_dma_init()
262 if (dev->hif2) in mt7996_dma_init()
263 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7996_dma_init()
268 ret = mt76_connac_init_tx_queues(dev->phy.mt76, in mt7996_dma_init()
269 MT_TXQ_ID(dev->mphy.band_idx), in mt7996_dma_init()
276 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, in mt7996_dma_init()
284 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA, in mt7996_dma_init()
292 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, in mt7996_dma_init()
300 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], in mt7996_dma_init()
309 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], in mt7996_dma_init()
318 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], in mt7996_dma_init()
327 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA], in mt7996_dma_init()
335 if (dev->tbtc_support || dev->mphy.band_idx == MT_BAND2) { in mt7996_dma_init()
337 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2], in mt7996_dma_init()
348 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2_WA], in mt7996_dma_init()
361 netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi, in mt7996_dma_init()
363 napi_enable(&dev->mt76.tx_napi); in mt7996_dma_init()
372 struct mt76_phy *phy2 = dev->mt76.phys[MT_BAND1]; in mt7996_dma_reset()
373 struct mt76_phy *phy3 = dev->mt76.phys[MT_BAND2]; in mt7996_dma_reset()
374 u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); in mt7996_dma_reset()
381 if (dev->hif2) in mt7996_dma_reset()
389 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); in mt7996_dma_reset()
391 mt76_queue_tx_cleanup(dev, phy2->q_tx[i], true); in mt7996_dma_reset()
393 mt76_queue_tx_cleanup(dev, phy3->q_tx[i], true); in mt7996_dma_reset()
397 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true); in mt7996_dma_reset()
399 mt76_for_each_q_rx(&dev->mt76, i) in mt7996_dma_reset()
400 mt76_queue_rx_cleanup(dev, &dev->mt76.q_rx[i]); in mt7996_dma_reset()
402 mt76_tx_status_check(&dev->mt76, true); in mt7996_dma_reset()
412 mt76_queue_reset(dev, dev->mphy.q_tx[i]); in mt7996_dma_reset()
414 mt76_queue_reset(dev, phy2->q_tx[i]); in mt7996_dma_reset()
416 mt76_queue_reset(dev, phy3->q_tx[i]); in mt7996_dma_reset()
420 mt76_queue_reset(dev, dev->mt76.q_mcu[i]); in mt7996_dma_reset()
422 mt76_for_each_q_rx(&dev->mt76, i) { in mt7996_dma_reset()
423 mt76_queue_reset(dev, &dev->mt76.q_rx[i]); in mt7996_dma_reset()
426 mt76_tx_status_check(&dev->mt76, true); in mt7996_dma_reset()
428 mt76_for_each_q_rx(&dev->mt76, i) in mt7996_dma_reset()
438 mt76_dma_cleanup(&dev->mt76); in mt7996_dma_cleanup()