Lines Matching +full:prefetch +full:- +full:dma
1 // SPDX-License-Identifier: ISC
8 #include "dma.h"
15 if (test_bit(MT76_REMOVED, &dev->mt76.phy.state)) in mt792x_irq_handler()
17 mt76_wr(dev, dev->irq_map->host_irq_enable, 0); in mt792x_irq_handler()
19 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) in mt792x_irq_handler()
22 tasklet_schedule(&dev->mt76.irq_tasklet); in mt792x_irq_handler()
31 const struct mt792x_irq_map *irq_map = dev->irq_map; in mt792x_irq_tasklet()
34 mt76_wr(dev, irq_map->host_irq_enable, 0); in mt792x_irq_tasklet()
37 intr &= dev->mt76.mmio.irqmask; in mt792x_irq_tasklet()
40 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt792x_irq_tasklet()
42 mask |= intr & (irq_map->rx.data_complete_mask | in mt792x_irq_tasklet()
43 irq_map->rx.wm_complete_mask | in mt792x_irq_tasklet()
44 irq_map->rx.wm2_complete_mask); in mt792x_irq_tasklet()
45 if (intr & dev->irq_map->tx.mcu_complete_mask) in mt792x_irq_tasklet()
46 mask |= dev->irq_map->tx.mcu_complete_mask; in mt792x_irq_tasklet()
55 mask |= irq_map->rx.data_complete_mask; in mt792x_irq_tasklet()
56 intr |= irq_map->rx.data_complete_mask; in mt792x_irq_tasklet()
60 mt76_set_irq_mask(&dev->mt76, irq_map->host_irq_enable, mask, 0); in mt792x_irq_tasklet()
62 if (intr & dev->irq_map->tx.all_complete_mask) in mt792x_irq_tasklet()
63 napi_schedule(&dev->mt76.tx_napi); in mt792x_irq_tasklet()
65 if (intr & irq_map->rx.wm_complete_mask) in mt792x_irq_tasklet()
66 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]); in mt792x_irq_tasklet()
68 if (intr & irq_map->rx.wm2_complete_mask) in mt792x_irq_tasklet()
69 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]); in mt792x_irq_tasklet()
71 if (intr & irq_map->rx.data_complete_mask) in mt792x_irq_tasklet()
72 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); in mt792x_irq_tasklet()
79 const struct mt792x_irq_map *irq_map = dev->irq_map; in mt792x_rx_poll_complete()
82 mt76_connac_irq_enable(mdev, irq_map->rx.data_complete_mask); in mt792x_rx_poll_complete()
84 mt76_connac_irq_enable(mdev, irq_map->rx.wm2_complete_mask); in mt792x_rx_poll_complete()
86 mt76_connac_irq_enable(mdev, irq_map->rx.wm_complete_mask); in mt792x_rx_poll_complete()
90 #define PREFETCH(base, depth) ((base) << 16 | (depth)) macro
93 mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4)); in mt792x_dma_prefetch()
94 mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x40, 0x4)); in mt792x_dma_prefetch()
95 mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x80, 0x4)); in mt792x_dma_prefetch()
96 mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0xc0, 0x4)); in mt792x_dma_prefetch()
97 mt76_wr(dev, MT_WFDMA0_RX_RING5_EXT_CTRL, PREFETCH(0x100, 0x4)); in mt792x_dma_prefetch()
99 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x140, 0x4)); in mt792x_dma_prefetch()
100 mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x180, 0x4)); in mt792x_dma_prefetch()
101 mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x1c0, 0x4)); in mt792x_dma_prefetch()
102 mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x200, 0x4)); in mt792x_dma_prefetch()
103 mt76_wr(dev, MT_WFDMA0_TX_RING4_EXT_CTRL, PREFETCH(0x240, 0x4)); in mt792x_dma_prefetch()
104 mt76_wr(dev, MT_WFDMA0_TX_RING5_EXT_CTRL, PREFETCH(0x280, 0x4)); in mt792x_dma_prefetch()
105 mt76_wr(dev, MT_WFDMA0_TX_RING6_EXT_CTRL, PREFETCH(0x2c0, 0x4)); in mt792x_dma_prefetch()
106 mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x340, 0x4)); in mt792x_dma_prefetch()
107 mt76_wr(dev, MT_WFDMA0_TX_RING17_EXT_CTRL, PREFETCH(0x380, 0x4)); in mt792x_dma_prefetch()
115 /* reset dma idx */ in mt792x_dma_enable()
135 mt76_connac_irq_enable(&dev->mt76, in mt792x_dma_enable()
136 dev->irq_map->tx.all_complete_mask | in mt792x_dma_enable()
137 dev->irq_map->rx.data_complete_mask | in mt792x_dma_enable()
138 dev->irq_map->rx.wm2_complete_mask | in mt792x_dma_enable()
139 dev->irq_map->rx.wm_complete_mask | in mt792x_dma_enable()
158 mt76_queue_reset(dev, dev->mphy.q_tx[i]); in mt792x_dma_reset()
161 mt76_queue_reset(dev, dev->mt76.q_mcu[i]); in mt792x_dma_reset()
163 mt76_for_each_q_rx(&dev->mt76, i) in mt792x_dma_reset()
164 mt76_queue_reset(dev, &dev->mt76.q_rx[i]); in mt792x_dma_reset()
166 mt76_tx_status_check(&dev->mt76, true); in mt792x_dma_reset()
176 for (i = 0; i < ARRAY_SIZE(dev->mt76.phy.q_tx); i++) in mt792x_wpdma_reset()
177 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); in mt792x_wpdma_reset()
179 for (i = 0; i < ARRAY_SIZE(dev->mt76.q_mcu); i++) in mt792x_wpdma_reset()
180 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true); in mt792x_wpdma_reset()
182 mt76_for_each_q_rx(&dev->mt76, i) in mt792x_wpdma_reset()
183 mt76_queue_rx_cleanup(dev, &dev->mt76.q_rx[i]); in mt792x_wpdma_reset()
194 mt76_for_each_q_rx(&dev->mt76, i) in mt792x_wpdma_reset()
203 struct mt76_connac_pm *pm = &dev->pm; in mt792x_wpdma_reinit_cond()
209 mt76_wr(dev, dev->irq_map->host_irq_enable, 0); in mt792x_wpdma_reinit_cond()
214 dev_err(dev->mt76.dev, "wpdma reset failed\n"); in mt792x_wpdma_reinit_cond()
220 pm->stats.lp_wake++; in mt792x_wpdma_reinit_cond()
240 return -ETIMEDOUT; in mt792x_dma_disable()
286 mt76_dma_cleanup(&dev->mt76); in mt792x_dma_cleanup()
296 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) { in mt792x_poll_tx()
298 queue_work(dev->mt76.wq, &dev->pm.wake_work); in mt792x_poll_tx()
302 mt76_connac_tx_cleanup(&dev->mt76); in mt792x_poll_tx()
304 mt76_connac_irq_enable(&dev->mt76, in mt792x_poll_tx()
305 dev->irq_map->tx.all_complete_mask); in mt792x_poll_tx()
306 mt76_connac_pm_unref(&dev->mphy, &dev->pm); in mt792x_poll_tx()
317 dev = container_of(napi->dev, struct mt792x_dev, mt76.napi_dev); in mt792x_poll_rx()
319 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) { in mt792x_poll_rx()
321 queue_work(dev->mt76.wq, &dev->pm.wake_work); in mt792x_poll_rx()
325 mt76_connac_pm_unref(&dev->mphy, &dev->pm); in mt792x_poll_rx()
333 u32 addr = is_mt7921(&dev->mt76) ? 0x18000140 : 0x7c000140; in mt792x_wfsys_reset()
339 if (!__mt76_poll_msec(&dev->mt76, addr, WFSYS_SW_INIT_DONE, in mt792x_wfsys_reset()
341 return -ETIMEDOUT; in mt792x_wfsys_reset()