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/openbmc/openbmc-test-automation/ipmi/
H A Dtest_ipmi_watchdog.robot60 Test IPMI Watchdog Timer Pre-Timeout Interrupt Bits
61 [Documentation] Execute out of band set/get pre-timeout interrupt bits for watchdog timer.
62 [Tags] Test_IPMI_Watchdog_Timer_Pre-Timeout_Interrupt_Bits
71 Test IPMI Watchdog Timer Timeout Action Bits
72 [Documentation] Execute out of band set/get timer timeout bits for watchdog timer.
86 Test IPMI Watchdog Timer Timeout Flag Bits
87 [Documentation] Execute out of band set/get timer timeout flag bits for watchdog timer.
134 # Start_timer_value is bits 6 - 7; set to 0x64 0x00 (100 ms decimal).
135 # Reverse bits 6 - 7 due to BMC being little endian; new value is 0x00 0x64.
160 Verify Pre-timeout Values
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/openbmc/libpldm/include/libpldm/
H A Dtransport.h1 /* SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later */
19 * @pre The pldm transport instance must be initialised; otherwise,
23 * @param[in] transport - Wait until this transport instance is ready
24 * @param[in] timeout - Wait for readiness for up to timeout milliseconds.
25 * Specifying a timeout value of zero yields an immediate return.
26 * Specifying a negative value means an indefinite timeout.
28 * @return 0 if a timeout occurs, 1 if the transport becomes ready, PLDM_REQUESTER_INVALID_SETUP if
31 int pldm_transport_poll(struct pldm_transport *transport, int timeout);
37 * @pre The pldm transport instance must be initialised; otherwise,
42 * @param[in] ctx - pldm transport instance
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/openbmc/linux/drivers/gpu/ipu-v3/
H A Dipu-pre.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <video/imx-ipu-v3.h>
15 #include "ipu-prv.h"
116 struct device_node *pre_node = of_parse_phandle(dev->of_node, in ipu_pre_lookup_by_phandle()
118 struct ipu_pre *pre; in ipu_pre_lookup_by_phandle() local
121 list_for_each_entry(pre, &ipu_pre_list, list) { in ipu_pre_lookup_by_phandle()
122 if (pre_node == pre->dev->of_node) { in ipu_pre_lookup_by_phandle()
124 device_link_add(dev, pre->dev, in ipu_pre_lookup_by_phandle()
127 return pre; in ipu_pre_lookup_by_phandle()
137 int ipu_pre_get(struct ipu_pre *pre) in ipu_pre_get() argument
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/openbmc/openbmc-test-automation/data/
H A Dipmi_raw_cmd_table.py6 - Define IPMI interface index, commands and expected output.
14 # openbmc/meta-openbmc-machines/meta-openpower/meta-ibm/meta-witherspoon/recipe
15 # s-phosphor/ipmi/phosphor-ipmi-host/cipher_list.json
162 "Last two bits are payload vlan number, - FFFFh if VLAN"
284 "pre-timeout interrupt None",
286 "pre-timeout interrupt NMI",
288 "timeout action None",
290 "timeout action Reset",
292 "timeout action PowerDown",
294 "timeout action PowerCycle",
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/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dmediatek,mtk-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/mediatek,mtk-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
13 The watchdog supports a pre-timeout interrupt that fires
14 timeout-sec/2 before the expiry.
17 - $ref: watchdog.yaml#
22 - enum:
23 - mediatek,mt2712-wdt
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H A Dnuvoton,npcm-wdt.txt3 Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog.
4 The watchdog supports a pre-timeout interrupt that fires 10ms before the
8 - compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg), or
9 "nuvoton,wpcm450-wdt" for WPCM450 (Hermon), or
10 "nuvoton,npcm845-wdt" for NPCM845 (Arbel).
11 - reg : Offset and length of the register set for the device.
12 - interrupts : Contain the timer interrupt with flags for
16 - clocks : phandle of timer reference clock.
17 - clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx
21 - timeout-sec : Contains the watchdog timeout in seconds
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/openbmc/linux/drivers/watchdog/
H A Ddw_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2010-2011 Picochip Ltd., Jamie Iles
7 * in the many subsystems. The watchdog has 16 different timeout periods
51 /* There are sixteen TOPs (timeout periods) that can be set in the watchdog. */
93 u32 timeout; member
104 return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) & in dw_wdt_is_enabled()
112 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); in dw_wdt_update_mode()
117 writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); in dw_wdt_update_mode()
119 dw_wdt->rmod = rmod; in dw_wdt_update_mode()
123 unsigned int timeout, u32 *top_val) in dw_wdt_find_best_top() argument
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H A Ddavinci_wdt.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2006-2013 Texas Instruments.
24 #define MODULE_NAME "DAVINCI-WDT: "
60 * @base - base io address of WD device
61 * @clk - source clock of WDT
62 * @wdd - hold watchdog device as is in WDT core
77 wdt_freq = clk_get_rate(davinci_wdt->clk); in davinci_wdt_start()
80 iowrite32(0, davinci_wdt->base + TCR); in davinci_wdt_start()
81 /* reset timer, set mode to 64-bit watchdog, and unreset */ in davinci_wdt_start()
82 iowrite32(0, davinci_wdt->base + TGCR); in davinci_wdt_start()
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H A Dlpc18xx_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * -----
9 * The Watchdog consists of a fixed divide-by-4 clock pre-scaler and a 24-bit
35 /* Clock pre-scaler */
38 /* Timeout values in seconds */
70 spin_lock_irqsave(&lpc18xx_wdt->lock, flags); in lpc18xx_wdt_feed()
71 writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED); in lpc18xx_wdt_feed()
72 writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED); in lpc18xx_wdt_feed()
73 spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags); in lpc18xx_wdt_feed()
81 struct watchdog_device *wdt_dev = &lpc18xx_wdt->wdt_dev; in lpc18xx_wdt_timer_feed()
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/openbmc/u-boot/arch/arm/dts/
H A Dbitmain-antminer-s9.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include "zynq-7000.dtsi"
13 compatible = "bitmain,antminer-s9", "xlnx,zynq-7000";
27 reserved-memory {
28 #address-cells = <1>;
29 #size-cells = <1>;
34 no-map;
39 no-map;
45 stdout-path = "serial0:115200n8";
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H A Dzynq-dlc20-rev1.0.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-dlc20-rev1.0", "xlnx,zynq-dlc20",
13 "xlnx,zynq-7000";
30 stdout-path = "serial0:115200n8";
34 compatible = "ulpi-phy";
35 #phy-cells = <0>;
37 view-port = <0x0170>;
38 drv-vbus;
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/openbmc/u-boot/drivers/fpga/
H A Dvirtex2.c1 // SPDX-License-Identifier: GPL-2.0+
30 * file and add board-specific support for checking BUSY status. By default,
60 * The default timeout in mS for INIT_B to deassert after PROG_B has
72 * The default timeout for waiting for BUSY to deassert during configuration.
80 /* Default timeout for waiting for FPGA to enter operational mode after
98 switch (desc->iface) { in virtex2_load()
111 __FUNCTION__, desc->iface); in virtex2_load()
120 switch (desc->iface) { in virtex2_dump()
133 __FUNCTION__, desc->iface); in virtex2_dump()
144 * Virtex-II Slave SelectMap configuration loader. Configuration via
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H A Dspartan2.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <common.h> /* core U-Boot definitions */
8 #include <spartan2.h> /* Spartan-II device family */
41 /* ------------------------------------------------------------------------- */
42 /* Spartan-II Generic Implementation */
48 switch (desc->iface) { in spartan2_load()
61 __FUNCTION__, desc->iface); in spartan2_load()
71 switch (desc->iface) { in spartan2_dump()
84 __FUNCTION__, desc->iface); in spartan2_dump()
96 /* ------------------------------------------------------------------------- */
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H A Dspartan3.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <common.h> /* core U-Boot definitions */
13 #include <spartan3.h> /* Spartan-II device family */
45 /* ------------------------------------------------------------------------- */
46 /* Spartan-II Generic Implementation */
52 switch (desc->iface) { in spartan3_load()
65 __FUNCTION__, desc->iface); in spartan3_load()
75 switch (desc->iface) { in spartan3_dump()
88 __FUNCTION__, desc->iface); in spartan3_dump()
100 /* ------------------------------------------------------------------------- */
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/openbmc/u-boot/include/configs/
H A Dintegrator-common.h1 /* SPDX-License-Identifier: GPL-2.0+ */
28 * then the U-Boot initialisation code will
29 * e.g. ARM Boot Monitor or pre-loader is repeated once
30 * (to re-initialise any existing CM_INIT settings to safe values).
33 * will either reboot into the ARM monitor (or pre-loader)
34 * or continuously cycle thru it without U-Boot running,
35 * depending upon the setting of Integrator/CP switch S2-4.
37 * However it may be needed if Integrator/CP switch S2-1
38 * is set OFF to boot direct into U-Boot.
47 * However, the default U-Boot code also performs the initialization.
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/openbmc/linux/drivers/gpu/drm/i915/selftests/
H A Dintel_scheduler_helpers.c1 // SPDX-License-Identifier: MIT
35 saved->reset = engine->i915->params.reset; in intel_selftest_modify_policy()
36 saved->flags = engine->flags; in intel_selftest_modify_policy()
37 saved->timeslice = engine->props.timeslice_duration_ms; in intel_selftest_modify_policy()
38 saved->preempt_timeout = engine->props.preempt_timeout_ms; in intel_selftest_modify_policy()
43 * Enable force pre-emption on time slice expiration in intel_selftest_modify_policy()
44 * together with engine reset on pre-emption timeout. in intel_selftest_modify_policy()
47 * Also, reduce the preemption timeout to something in intel_selftest_modify_policy()
50 engine->i915->params.reset = 2; in intel_selftest_modify_policy()
51 engine->flags |= I915_ENGINE_WANT_FORCED_PREEMPTION; in intel_selftest_modify_policy()
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/openbmc/phosphor-state-manager/target_files/
H A Dmeson.build2 'obmc-bmc-service-quiesce@.target',
3 'obmc-chassis-blackout@.target',
4 'obmc-chassis-hard-poweroff@.target',
5 'obmc-chassis-powered-off@.target',
6 'obmc-chassis-poweroff@.target',
7 'obmc-chassis-poweron@.target',
8 'obmc-chassis-powerreset@.target',
9 'obmc-chassis-powercycle@.target',
10 'obmc-fan-control-ready@.target',
11 'obmc-fan-control.target',
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/openbmc/openbmc/meta-phosphor/recipes-phosphor/state/
H A Dphosphor-state-manager_git.bb5 HOMEPAGE = "https://github.com/openbmc/phosphor-state-manager"
8 LICENSE = "Apache-2.0"
11 include phosphor-state-manager-systemd-links.inc
14 ${PN}-host \
15 ${PN}-chassis \
16 ${PN}-bmc \
17 ${PN}-hypervisor \
18 ${PN}-discover \
19 ${PN}-host-check \
20 ${PN}-reset-sensor-states \
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/openbmc/linux/drivers/clk/samsung/
H A Dclk-cpu.c1 // SPDX-License-Identifier: GPL-2.0-only
22 * registers to acheive a fast co-oridinated rate change for all the CPU domain
36 #include <linux/clk-provider.h>
37 #include "clk-cpu.h"
71 unsigned long timeout = jiffies + msecs_to_jiffies(10); in wait_until_divider_stable() local
76 } while (time_before(jiffies, timeout)); in wait_until_divider_stable()
81 pr_err("%s: timeout in divider stablization\n", __func__); in wait_until_divider_stable()
91 unsigned long timeout = jiffies + msecs_to_jiffies(10); in wait_until_mux_stable() local
96 } while (time_before(jiffies, timeout)); in wait_until_mux_stable()
101 pr_err("%s: re-parenting mux timed-out\n", __func__); in wait_until_mux_stable()
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/openbmc/linux/drivers/media/dvb-frontends/
H A Ddrxk_hard.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define SCU_RESULT_SIZE -4
25 #define SCU_RESULT_INVPAR -3
26 #define SCU_RESULT_UNKSTD -2
27 #define SCU_RESULT_UNKCMD -1
189 u16 top; /* rf-agc take over point */
190 u16 cut_off_current; /* rf-agc is accelerated if output current
191 is below cut-off current */
197 u16 reference; /* pre SAW reference value, range 0 .. 31 */
198 bool use_pre_saw; /* TRUE algorithms must use pre SAW sense */
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-dbs/mysql/mariadb/
H A Dmysql-systemd-start3 # Needed argument: pre | post
5 # pre mode : try to run mysql_install_db and fix perms and SELinux contexts
13 ret=$(/usr/bin/my_print_defaults $section | grep '^--'${option}'=' | cut -d= -f2-)
14 [ -z $ret ] && ret=$default
23 [ -d "$datadir" ] || install -d -m 0755 -omysql -gmysql "$datadir" || exit 1
25 [ -e $log ] || touch $log
28 if [ -x /usr/sbin/restorecon ]; then
34 [ -d "$datadir/mysql" ] && exit 0
37 /usr/bin/mysql_install_db --rpm --datadir="$datadir" --user=mysql
44 # MySQL systemd service will timeout script if no answer
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/openbmc/linux/drivers/input/touchscreen/
H A Dimx6ul_tsc.c1 // SPDX-License-Identifier: GPL-2.0
109 unsigned long timeout; in imx6ul_adc_init() local
111 reinit_completion(&tsc->completion); in imx6ul_adc_init()
113 adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG); in imx6ul_adc_init()
118 if (tsc->average_enable) { in imx6ul_adc_init()
120 adc_cfg |= (tsc->average_select) << ADC_AVGS_SHIFT; in imx6ul_adc_init()
123 writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG); in imx6ul_adc_init()
128 writel(adc_hc, tsc->adc_regs + REG_ADC_HC0); in imx6ul_adc_init()
131 adc_gc = readl(tsc->adc_regs + REG_ADC_GC); in imx6ul_adc_init()
133 if (tsc->average_enable) in imx6ul_adc_init()
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/openbmc/linux/drivers/net/wireless/ath/ath5k/
H A Dpci.c2 * Copyright (c) 2008-2009 Atheros Communications Inc.
33 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
45 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
47 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
59 struct ath5k_hw *ah = (struct ath5k_hw *) common->priv; in ath5k_pci_read_cachesize()
62 pci_read_config_byte(ah->pdev, PCI_CACHE_LINE_SIZE, &u8tmp); in ath5k_pci_read_cachesize()
81 struct ath5k_hw *ah = (struct ath5k_hw *) common->ah; in ath5k_pci_eeprom_read()
82 u32 status, timeout; in ath5k_pci_eeprom_read() local
87 if (ah->ah_version == AR5K_AR5210) { in ath5k_pci_eeprom_read()
96 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { in ath5k_pci_eeprom_read()
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/openbmc/linux/drivers/i2c/busses/
H A Di2c-ali1563.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-ali1563.c - i2c driver for the ALi 1563 Southbridge
68 int timeout; in ali1563_transaction() local
69 int status = -EIO; in ali1563_transaction()
71 dev_dbg(&a->dev, "Transaction (pre): STS=%02x, CNTL1=%02x, " in ali1563_transaction()
79 dev_err(&a->dev, "ali1563: Trying to reset busy device\n"); in ali1563_transaction()
83 return -EBUSY; in ali1563_transaction()
87 timeout = ALI1563_MAX_TIMEOUT; in ali1563_transaction()
90 } while (((data = inb_p(SMB_HST_STS)) & HST_STS_BUSY) && --timeout); in ali1563_transaction()
92 dev_dbg(&a->dev, "Transaction (post): STS=%02x, CNTL1=%02x, " in ali1563_transaction()
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/openbmc/linux/drivers/accel/ivpu/
H A Divpu_pm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2023 Intel Corporation
29 struct ivpu_fw_info *fw = vdev->fw; in ivpu_pm_prepare_cold_boot()
34 fw->entry_point = fw->cold_boot_entry_point; in ivpu_pm_prepare_cold_boot()
39 struct ivpu_fw_info *fw = vdev->fw; in ivpu_pm_prepare_warm_boot()
40 struct vpu_boot_params *bp = fw->mem->kvaddr; in ivpu_pm_prepare_warm_boot()
42 if (!bp->save_restore_ret_address) { in ivpu_pm_prepare_warm_boot()
47 ivpu_dbg(vdev, FW_BOOT, "Save/restore entry point %llx", bp->save_restore_ret_address); in ivpu_pm_prepare_warm_boot()
48 fw->entry_point = bp->save_restore_ret_address; in ivpu_pm_prepare_warm_boot()
101 struct ivpu_device *vdev = pm->vdev; in ivpu_pm_recovery_work()
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