1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Copyright 2010-2011 Picochip Ltd., Jamie Iles
7  * in the many subsystems. The watchdog has 16 different timeout periods
51 /* There are sixteen TOPs (timeout periods) that can be set in the watchdog. */
93 	u32			timeout;  member
104 	return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &  in dw_wdt_is_enabled()
112 	val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);  in dw_wdt_update_mode()
117 	writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);  in dw_wdt_update_mode()
119 	dw_wdt->rmod = rmod;  in dw_wdt_update_mode()
123 					 unsigned int timeout, u32 *top_val)  in dw_wdt_find_best_top()  argument
128 	 * Find a TOP with timeout greater or equal to the requested number.  in dw_wdt_find_best_top()
129 	 * Note we'll select a TOP with maximum timeout if the requested  in dw_wdt_find_best_top()
130 	 * timeout couldn't be reached.  in dw_wdt_find_best_top()
133 		if (dw_wdt->timeouts[idx].sec >= timeout)  in dw_wdt_find_best_top()
138 		--idx;  in dw_wdt_find_best_top()
140 	*top_val = dw_wdt->timeouts[idx].top_val;  in dw_wdt_find_best_top()
142 	return dw_wdt->timeouts[idx].sec;  in dw_wdt_find_best_top()
150 	 * We'll find a timeout greater or equal to one second anyway because  in dw_wdt_get_min_timeout()
154 		if (dw_wdt->timeouts[idx].sec)  in dw_wdt_get_min_timeout()
158 	return dw_wdt->timeouts[idx].sec;  in dw_wdt_get_min_timeout()
163 	struct dw_wdt_timeout *timeout = &dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1];  in dw_wdt_get_max_timeout_ms()  local
166 	msec = (u64)timeout->sec * MSEC_PER_SEC + timeout->msec;  in dw_wdt_get_max_timeout_ms()
173 	int top_val = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;  in dw_wdt_get_timeout()
177 		if (dw_wdt->timeouts[idx].top_val == top_val)  in dw_wdt_get_timeout()
182 	 * In IRQ mode due to the two stages counter, the actual timeout is  in dw_wdt_get_timeout()
185 	return dw_wdt->timeouts[idx].sec * dw_wdt->rmod;  in dw_wdt_get_timeout()
192 	writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +  in dw_wdt_ping()
201 	unsigned int timeout;  in dw_wdt_set_timeout()  local
205 	 * Note IRQ mode being enabled means having a non-zero pre-timeout  in dw_wdt_set_timeout()
207 	 * requested timeout as possible since DW Watchdog IRQ mode is designed  in dw_wdt_set_timeout()
208 	 * in two stages way - first timeout rises the pre-timeout interrupt,  in dw_wdt_set_timeout()
209 	 * second timeout performs the system reset. So basically the effective  in dw_wdt_set_timeout()
210 	 * watchdog-caused reset happens after two watchdog TOPs elapsed.  in dw_wdt_set_timeout()
212 	timeout = dw_wdt_find_best_top(dw_wdt, DIV_ROUND_UP(top_s, dw_wdt->rmod),  in dw_wdt_set_timeout()
214 	if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)  in dw_wdt_set_timeout()
215 		wdd->pretimeout = timeout;  in dw_wdt_set_timeout()
217 		wdd->pretimeout = 0;  in dw_wdt_set_timeout()
226 	       dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);  in dw_wdt_set_timeout()
233 	 * In case users set bigger timeout value than HW can support,  in dw_wdt_set_timeout()
235 	 * wdd->max_hw_heartbeat_ms  in dw_wdt_set_timeout()
237 	if (top_s * 1000 <= wdd->max_hw_heartbeat_ms)  in dw_wdt_set_timeout()
238 		wdd->timeout = timeout * dw_wdt->rmod;  in dw_wdt_set_timeout()
240 		wdd->timeout = top_s;  in dw_wdt_set_timeout()
250 	 * We ignore actual value of the timeout passed from user-space  in dw_wdt_set_pretimeout()
255 	dw_wdt_set_timeout(wdd, wdd->timeout);  in dw_wdt_set_pretimeout()
262 	u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);  in dw_wdt_arm_system_reset()
265 	if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)  in dw_wdt_arm_system_reset()
271 	writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);  in dw_wdt_arm_system_reset()
278 	dw_wdt_set_timeout(wdd, wdd->timeout);  in dw_wdt_start()
279 	dw_wdt_ping(&dw_wdt->wdd);  in dw_wdt_start()
289 	if (!dw_wdt->rst) {  in dw_wdt_stop()
290 		set_bit(WDOG_HW_RUNNING, &wdd->status);  in dw_wdt_stop()
294 	reset_control_assert(dw_wdt->rst);  in dw_wdt_stop()
295 	reset_control_deassert(dw_wdt->rst);  in dw_wdt_stop()
305 	writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);  in dw_wdt_restart()
309 		       dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);  in dw_wdt_restart()
325 	val = readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET);  in dw_wdt_get_timeleft()
326 	sec = val / dw_wdt->rate;  in dw_wdt_get_timeleft()
328 	if (dw_wdt->rmod == DW_WDT_RMOD_IRQ) {  in dw_wdt_get_timeleft()
329 		val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);  in dw_wdt_get_timeleft()
331 			sec += wdd->pretimeout;  in dw_wdt_get_timeleft()
369 	val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);  in dw_wdt_irq()
373 	watchdog_notify_pretimeout(&dw_wdt->wdd);  in dw_wdt_irq()
382 	dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);  in dw_wdt_suspend()
383 	dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);  in dw_wdt_suspend()
385 	clk_disable_unprepare(dw_wdt->pclk);  in dw_wdt_suspend()
386 	clk_disable_unprepare(dw_wdt->clk);  in dw_wdt_suspend()
394 	int err = clk_prepare_enable(dw_wdt->clk);  in dw_wdt_resume()
399 	err = clk_prepare_enable(dw_wdt->pclk);  in dw_wdt_resume()
401 		clk_disable_unprepare(dw_wdt->clk);  in dw_wdt_resume()
405 	writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);  in dw_wdt_resume()
406 	writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);  in dw_wdt_resume()
408 	dw_wdt_ping(&dw_wdt->wdd);  in dw_wdt_resume()
419  * passed TOPs array to pre-calculate the effective timeouts and to sort the
437 		tout.sec = tops[val] / dw_wdt->rate;  in dw_wdt_handle_tops()
439 		do_div(msec, dw_wdt->rate);  in dw_wdt_handle_tops()
440 		tout.msec = msec - ((u64)tout.sec * MSEC_PER_SEC);  in dw_wdt_handle_tops()
447 			dst = &dw_wdt->timeouts[tidx];  in dw_wdt_handle_tops()
448 			if (tout.sec > dst->sec || (tout.sec == dst->sec &&  in dw_wdt_handle_tops()
449 			    tout.msec >= dst->msec))  in dw_wdt_handle_tops()
455 		dw_wdt->timeouts[val] = tout;  in dw_wdt_handle_tops()
470 	data = readl(dw_wdt->regs + WDOG_COMP_PARAMS_1_REG_OFFSET);  in dw_wdt_init_timeouts()
475 			"snps,watchdog-tops", of_tops, DW_WDT_NUM_TOPS,  in dw_wdt_init_timeouts()
487 	if (!dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1].sec) {  in dw_wdt_init_timeouts()
489 		return -EINVAL;  in dw_wdt_init_timeouts()
520 	struct device *dev = dw_wdt->wdd.parent;  in dw_wdt_dbgfs_init()
527 	regset->regs = dw_wdt_dbgfs_regs;  in dw_wdt_dbgfs_init()
528 	regset->nregs = ARRAY_SIZE(dw_wdt_dbgfs_regs);  in dw_wdt_dbgfs_init()
529 	regset->base = dw_wdt->regs;  in dw_wdt_dbgfs_init()
531 	dw_wdt->dbgfs_dir = debugfs_create_dir(dev_name(dev), NULL);  in dw_wdt_dbgfs_init()
533 	debugfs_create_regset32("registers", 0444, dw_wdt->dbgfs_dir, regset);  in dw_wdt_dbgfs_init()
538 	debugfs_remove_recursive(dw_wdt->dbgfs_dir);  in dw_wdt_dbgfs_clear()
550 	struct device *dev = &pdev->dev;  in dw_wdt_drv_probe()
557 		return -ENOMEM;  in dw_wdt_drv_probe()
559 	dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0);  in dw_wdt_drv_probe()
560 	if (IS_ERR(dw_wdt->regs))  in dw_wdt_drv_probe()
561 		return PTR_ERR(dw_wdt->regs);  in dw_wdt_drv_probe()
569 	dw_wdt->clk = devm_clk_get_enabled(dev, "tclk");  in dw_wdt_drv_probe()
570 	if (IS_ERR(dw_wdt->clk)) {  in dw_wdt_drv_probe()
571 		dw_wdt->clk = devm_clk_get_enabled(dev, NULL);  in dw_wdt_drv_probe()
572 		if (IS_ERR(dw_wdt->clk))  in dw_wdt_drv_probe()
573 			return PTR_ERR(dw_wdt->clk);  in dw_wdt_drv_probe()
576 	dw_wdt->rate = clk_get_rate(dw_wdt->clk);  in dw_wdt_drv_probe()
577 	if (dw_wdt->rate == 0)  in dw_wdt_drv_probe()
578 		return -EINVAL;  in dw_wdt_drv_probe()
587 	dw_wdt->pclk = devm_clk_get_optional_enabled(dev, "pclk");  in dw_wdt_drv_probe()
588 	if (IS_ERR(dw_wdt->pclk))  in dw_wdt_drv_probe()
589 		return PTR_ERR(dw_wdt->pclk);  in dw_wdt_drv_probe()
591 	dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);  in dw_wdt_drv_probe()
592 	if (IS_ERR(dw_wdt->rst))  in dw_wdt_drv_probe()
593 		return PTR_ERR(dw_wdt->rst);  in dw_wdt_drv_probe()
595 	/* Enable normal reset without pre-timeout by default. */  in dw_wdt_drv_probe()
599 	 * Pre-timeout IRQ is optional, since some hardware may lack support  in dw_wdt_drv_probe()
600 	 * of it. Note we must request rising-edge IRQ, since the lane is left  in dw_wdt_drv_probe()
608 				       pdev->name, dw_wdt);  in dw_wdt_drv_probe()
612 		dw_wdt->wdd.info = &dw_wdt_pt_ident;  in dw_wdt_drv_probe()
614 		if (ret == -EPROBE_DEFER)  in dw_wdt_drv_probe()
617 		dw_wdt->wdd.info = &dw_wdt_ident;  in dw_wdt_drv_probe()
620 	reset_control_deassert(dw_wdt->rst);  in dw_wdt_drv_probe()
626 	wdd = &dw_wdt->wdd;  in dw_wdt_drv_probe()
627 	wdd->ops = &dw_wdt_ops;  in dw_wdt_drv_probe()
628 	wdd->min_timeout = dw_wdt_get_min_timeout(dw_wdt);  in dw_wdt_drv_probe()
629 	wdd->max_hw_heartbeat_ms = dw_wdt_get_max_timeout_ms(dw_wdt);  in dw_wdt_drv_probe()
630 	wdd->parent = dev;  in dw_wdt_drv_probe()
638 	 * timeout. Otherwise use the default or the value provided through  in dw_wdt_drv_probe()
642 		wdd->timeout = dw_wdt_get_timeout(dw_wdt);  in dw_wdt_drv_probe()
643 		set_bit(WDOG_HW_RUNNING, &wdd->status);  in dw_wdt_drv_probe()
645 		wdd->timeout = DW_WDT_DEFAULT_SECONDS;  in dw_wdt_drv_probe()
663 	reset_control_assert(dw_wdt->rst);  in dw_wdt_drv_probe()
673 	watchdog_unregister_device(&dw_wdt->wdd);  in dw_wdt_drv_remove()
674 	reset_control_assert(dw_wdt->rst);  in dw_wdt_drv_remove()
679 	{ .compatible = "snps,dw-wdt", },