12025cf9eSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2d2a34232SLucas Stach /*
3d2a34232SLucas Stach * Copyright (c) 2017 Lucas Stach, Pengutronix
4d2a34232SLucas Stach */
5d2a34232SLucas Stach
6d2a34232SLucas Stach #include <drm/drm_fourcc.h>
7d2a34232SLucas Stach #include <linux/clk.h>
8d2a34232SLucas Stach #include <linux/err.h>
9d2a34232SLucas Stach #include <linux/genalloc.h>
10d2a34232SLucas Stach #include <linux/module.h>
11d2a34232SLucas Stach #include <linux/of.h>
12d2a34232SLucas Stach #include <linux/platform_device.h>
13d2a34232SLucas Stach #include <video/imx-ipu-v3.h>
14d2a34232SLucas Stach
15d2a34232SLucas Stach #include "ipu-prv.h"
16d2a34232SLucas Stach
17d2a34232SLucas Stach #define IPU_PRE_MAX_WIDTH 2048
18d2a34232SLucas Stach #define IPU_PRE_NUM_SCANLINES 8
19d2a34232SLucas Stach
20d2a34232SLucas Stach #define IPU_PRE_CTRL 0x000
21d2a34232SLucas Stach #define IPU_PRE_CTRL_SET 0x004
22d2a34232SLucas Stach #define IPU_PRE_CTRL_ENABLE (1 << 0)
23d2a34232SLucas Stach #define IPU_PRE_CTRL_BLOCK_EN (1 << 1)
24d2a34232SLucas Stach #define IPU_PRE_CTRL_BLOCK_16 (1 << 2)
25d2a34232SLucas Stach #define IPU_PRE_CTRL_SDW_UPDATE (1 << 4)
26d2a34232SLucas Stach #define IPU_PRE_CTRL_VFLIP (1 << 5)
27d2a34232SLucas Stach #define IPU_PRE_CTRL_SO (1 << 6)
28d2a34232SLucas Stach #define IPU_PRE_CTRL_INTERLACED_FIELD (1 << 7)
29d2a34232SLucas Stach #define IPU_PRE_CTRL_HANDSHAKE_EN (1 << 8)
30d2a34232SLucas Stach #define IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v) ((v & 0x3) << 9)
31d2a34232SLucas Stach #define IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN (1 << 11)
32d2a34232SLucas Stach #define IPU_PRE_CTRL_EN_REPEAT (1 << 28)
33d2a34232SLucas Stach #define IPU_PRE_CTRL_TPR_REST_SEL (1 << 29)
34d2a34232SLucas Stach #define IPU_PRE_CTRL_CLKGATE (1 << 30)
35d2a34232SLucas Stach #define IPU_PRE_CTRL_SFTRST (1 << 31)
36d2a34232SLucas Stach
37d2a34232SLucas Stach #define IPU_PRE_CUR_BUF 0x030
38d2a34232SLucas Stach
39d2a34232SLucas Stach #define IPU_PRE_NEXT_BUF 0x040
40d2a34232SLucas Stach
41d2a34232SLucas Stach #define IPU_PRE_TPR_CTRL 0x070
42d2a34232SLucas Stach #define IPU_PRE_TPR_CTRL_TILE_FORMAT(v) ((v & 0xff) << 0)
43d2a34232SLucas Stach #define IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK 0xff
442f64a554SLucas Stach #define IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT (1 << 0)
452f64a554SLucas Stach #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SPLIT_BUF (1 << 4)
462f64a554SLucas Stach #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF (1 << 5)
472f64a554SLucas Stach #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED (1 << 6)
48d2a34232SLucas Stach
49d2a34232SLucas Stach #define IPU_PRE_PREFETCH_ENG_CTRL 0x080
50d2a34232SLucas Stach #define IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN (1 << 0)
51d2a34232SLucas Stach #define IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v) ((v & 0x7) << 1)
52d2a34232SLucas Stach #define IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v) ((v & 0x3) << 4)
53d2a34232SLucas Stach #define IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v) ((v & 0x7) << 8)
54d2a34232SLucas Stach #define IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS (1 << 11)
55d2a34232SLucas Stach #define IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE (1 << 12)
56d2a34232SLucas Stach #define IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP (1 << 14)
57d2a34232SLucas Stach #define IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN (1 << 15)
58d2a34232SLucas Stach
59d2a34232SLucas Stach #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE 0x0a0
60d2a34232SLucas Stach #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v) ((v & 0xffff) << 0)
61d2a34232SLucas Stach #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v) ((v & 0xffff) << 16)
62d2a34232SLucas Stach
63d2a34232SLucas Stach #define IPU_PRE_PREFETCH_ENG_PITCH 0x0d0
64d2a34232SLucas Stach #define IPU_PRE_PREFETCH_ENG_PITCH_Y(v) ((v & 0xffff) << 0)
65d2a34232SLucas Stach #define IPU_PRE_PREFETCH_ENG_PITCH_UV(v) ((v & 0xffff) << 16)
66d2a34232SLucas Stach
67d2a34232SLucas Stach #define IPU_PRE_STORE_ENG_CTRL 0x110
68d2a34232SLucas Stach #define IPU_PRE_STORE_ENG_CTRL_STORE_EN (1 << 0)
69d2a34232SLucas Stach #define IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v) ((v & 0x7) << 1)
70d2a34232SLucas Stach #define IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v) ((v & 0x3) << 4)
71d2a34232SLucas Stach
7211aff4b4SLucas Stach #define IPU_PRE_STORE_ENG_STATUS 0x120
7311aff4b4SLucas Stach #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_MASK 0xffff
7411aff4b4SLucas Stach #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_SHIFT 0
7511aff4b4SLucas Stach #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK 0x3fff
7611aff4b4SLucas Stach #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT 16
7711aff4b4SLucas Stach #define IPU_PRE_STORE_ENG_STATUS_STORE_FIFO_FULL (1 << 30)
7811aff4b4SLucas Stach #define IPU_PRE_STORE_ENG_STATUS_STORE_FIELD (1 << 31)
7911aff4b4SLucas Stach
80d2a34232SLucas Stach #define IPU_PRE_STORE_ENG_SIZE 0x130
81d2a34232SLucas Stach #define IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v) ((v & 0xffff) << 0)
82d2a34232SLucas Stach #define IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v) ((v & 0xffff) << 16)
83d2a34232SLucas Stach
84d2a34232SLucas Stach #define IPU_PRE_STORE_ENG_PITCH 0x140
85d2a34232SLucas Stach #define IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v) ((v & 0xffff) << 0)
86d2a34232SLucas Stach
87d2a34232SLucas Stach #define IPU_PRE_STORE_ENG_ADDR 0x150
88d2a34232SLucas Stach
89d2a34232SLucas Stach struct ipu_pre {
90d2a34232SLucas Stach struct list_head list;
91d2a34232SLucas Stach struct device *dev;
92d2a34232SLucas Stach
93d2a34232SLucas Stach void __iomem *regs;
94d2a34232SLucas Stach struct clk *clk_axi;
95d2a34232SLucas Stach struct gen_pool *iram;
96d2a34232SLucas Stach
97d2a34232SLucas Stach dma_addr_t buffer_paddr;
98d2a34232SLucas Stach void *buffer_virt;
99d2a34232SLucas Stach bool in_use;
10011aff4b4SLucas Stach unsigned int safe_window_end;
101eb0200a4SLucas Stach unsigned int last_bufaddr;
102d2a34232SLucas Stach };
103d2a34232SLucas Stach
104d2a34232SLucas Stach static DEFINE_MUTEX(ipu_pre_list_mutex);
105d2a34232SLucas Stach static LIST_HEAD(ipu_pre_list);
106d2a34232SLucas Stach static int available_pres;
107d2a34232SLucas Stach
ipu_pre_get_available_count(void)108d2a34232SLucas Stach int ipu_pre_get_available_count(void)
109d2a34232SLucas Stach {
110d2a34232SLucas Stach return available_pres;
111d2a34232SLucas Stach }
112d2a34232SLucas Stach
113d2a34232SLucas Stach struct ipu_pre *
ipu_pre_lookup_by_phandle(struct device * dev,const char * name,int index)114d2a34232SLucas Stach ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index)
115d2a34232SLucas Stach {
116d2a34232SLucas Stach struct device_node *pre_node = of_parse_phandle(dev->of_node,
117d2a34232SLucas Stach name, index);
118d2a34232SLucas Stach struct ipu_pre *pre;
119d2a34232SLucas Stach
120d2a34232SLucas Stach mutex_lock(&ipu_pre_list_mutex);
121d2a34232SLucas Stach list_for_each_entry(pre, &ipu_pre_list, list) {
122d2a34232SLucas Stach if (pre_node == pre->dev->of_node) {
123d2a34232SLucas Stach mutex_unlock(&ipu_pre_list_mutex);
124e88728f4SVivek Gautam device_link_add(dev, pre->dev,
125e88728f4SVivek Gautam DL_FLAG_AUTOREMOVE_CONSUMER);
126c795f305STobias Jordan of_node_put(pre_node);
127d2a34232SLucas Stach return pre;
128d2a34232SLucas Stach }
129d2a34232SLucas Stach }
130d2a34232SLucas Stach mutex_unlock(&ipu_pre_list_mutex);
131d2a34232SLucas Stach
132c795f305STobias Jordan of_node_put(pre_node);
133c795f305STobias Jordan
134d2a34232SLucas Stach return NULL;
135d2a34232SLucas Stach }
136d2a34232SLucas Stach
ipu_pre_get(struct ipu_pre * pre)137d2a34232SLucas Stach int ipu_pre_get(struct ipu_pre *pre)
138d2a34232SLucas Stach {
139d2a34232SLucas Stach u32 val;
140d2a34232SLucas Stach
141d2a34232SLucas Stach if (pre->in_use)
142d2a34232SLucas Stach return -EBUSY;
143d2a34232SLucas Stach
144d2a34232SLucas Stach /* first get the engine out of reset and remove clock gating */
145d2a34232SLucas Stach writel(0, pre->regs + IPU_PRE_CTRL);
146d2a34232SLucas Stach
147d2a34232SLucas Stach /* init defaults that should be applied to all streams */
148d2a34232SLucas Stach val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN |
149d2a34232SLucas Stach IPU_PRE_CTRL_HANDSHAKE_EN |
150d2a34232SLucas Stach IPU_PRE_CTRL_TPR_REST_SEL |
1512f64a554SLucas Stach IPU_PRE_CTRL_SDW_UPDATE;
152d2a34232SLucas Stach writel(val, pre->regs + IPU_PRE_CTRL);
153d2a34232SLucas Stach
154d2a34232SLucas Stach pre->in_use = true;
155d2a34232SLucas Stach return 0;
156d2a34232SLucas Stach }
157d2a34232SLucas Stach
ipu_pre_put(struct ipu_pre * pre)158d2a34232SLucas Stach void ipu_pre_put(struct ipu_pre *pre)
159d2a34232SLucas Stach {
16047c298f7SLucas Stach writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL);
161d2a34232SLucas Stach
162d2a34232SLucas Stach pre->in_use = false;
163d2a34232SLucas Stach }
164d2a34232SLucas Stach
ipu_pre_configure(struct ipu_pre * pre,unsigned int width,unsigned int height,unsigned int stride,u32 format,uint64_t modifier,unsigned int bufaddr)165d2a34232SLucas Stach void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
166d2a34232SLucas Stach unsigned int height, unsigned int stride, u32 format,
1672f64a554SLucas Stach uint64_t modifier, unsigned int bufaddr)
168d2a34232SLucas Stach {
169d2a34232SLucas Stach const struct drm_format_info *info = drm_format_info(format);
170d2a34232SLucas Stach u32 active_bpp = info->cpp[0] >> 1;
171d2a34232SLucas Stach u32 val;
172d2a34232SLucas Stach
17311aff4b4SLucas Stach /* calculate safe window for ctrl register updates */
1742f64a554SLucas Stach if (modifier == DRM_FORMAT_MOD_LINEAR)
17511aff4b4SLucas Stach pre->safe_window_end = height - 2;
1762f64a554SLucas Stach else
1772f64a554SLucas Stach pre->safe_window_end = DIV_ROUND_UP(height, 4) - 1;
17811aff4b4SLucas Stach
179d2a34232SLucas Stach writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
180d2a34232SLucas Stach writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
181eb0200a4SLucas Stach pre->last_bufaddr = bufaddr;
182d2a34232SLucas Stach
183d2a34232SLucas Stach val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) |
184d2a34232SLucas Stach IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) |
185d2a34232SLucas Stach IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) |
186d2a34232SLucas Stach IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS |
187d2a34232SLucas Stach IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN;
188d2a34232SLucas Stach writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL);
189d2a34232SLucas Stach
190d2a34232SLucas Stach val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) |
191d2a34232SLucas Stach IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height);
192d2a34232SLucas Stach writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE);
193d2a34232SLucas Stach
194d2a34232SLucas Stach val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride);
195d2a34232SLucas Stach writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH);
196d2a34232SLucas Stach
197d2a34232SLucas Stach val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) |
198d2a34232SLucas Stach IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) |
199d2a34232SLucas Stach IPU_PRE_STORE_ENG_CTRL_STORE_EN;
200d2a34232SLucas Stach writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL);
201d2a34232SLucas Stach
202d2a34232SLucas Stach val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) |
203d2a34232SLucas Stach IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height);
204d2a34232SLucas Stach writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE);
205d2a34232SLucas Stach
206d2a34232SLucas Stach val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride);
207d2a34232SLucas Stach writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH);
208d2a34232SLucas Stach
209d2a34232SLucas Stach writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR);
210d2a34232SLucas Stach
2112f64a554SLucas Stach val = readl(pre->regs + IPU_PRE_TPR_CTRL);
2122f64a554SLucas Stach val &= ~IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK;
2132f64a554SLucas Stach if (modifier != DRM_FORMAT_MOD_LINEAR) {
2142f64a554SLucas Stach /* only support single buffer formats for now */
2152f64a554SLucas Stach val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF;
2162f64a554SLucas Stach if (modifier == DRM_FORMAT_MOD_VIVANTE_SUPER_TILED)
2172f64a554SLucas Stach val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED;
2182f64a554SLucas Stach if (info->cpp[0] == 2)
2192f64a554SLucas Stach val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT;
2202f64a554SLucas Stach }
2212f64a554SLucas Stach writel(val, pre->regs + IPU_PRE_TPR_CTRL);
2222f64a554SLucas Stach
223d2a34232SLucas Stach val = readl(pre->regs + IPU_PRE_CTRL);
224d2a34232SLucas Stach val |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE |
225d2a34232SLucas Stach IPU_PRE_CTRL_SDW_UPDATE;
2262f64a554SLucas Stach if (modifier == DRM_FORMAT_MOD_LINEAR)
2272f64a554SLucas Stach val &= ~IPU_PRE_CTRL_BLOCK_EN;
2282f64a554SLucas Stach else
2292f64a554SLucas Stach val |= IPU_PRE_CTRL_BLOCK_EN;
230d2a34232SLucas Stach writel(val, pre->regs + IPU_PRE_CTRL);
231d2a34232SLucas Stach }
232d2a34232SLucas Stach
ipu_pre_update(struct ipu_pre * pre,unsigned int bufaddr)233d2a34232SLucas Stach void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr)
234d2a34232SLucas Stach {
23511aff4b4SLucas Stach unsigned long timeout = jiffies + msecs_to_jiffies(5);
23611aff4b4SLucas Stach unsigned short current_yblock;
23711aff4b4SLucas Stach u32 val;
23811aff4b4SLucas Stach
239eb0200a4SLucas Stach if (bufaddr == pre->last_bufaddr)
240eb0200a4SLucas Stach return;
241eb0200a4SLucas Stach
242d2a34232SLucas Stach writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
243eb0200a4SLucas Stach pre->last_bufaddr = bufaddr;
24411aff4b4SLucas Stach
24511aff4b4SLucas Stach do {
24611aff4b4SLucas Stach if (time_after(jiffies, timeout)) {
24711aff4b4SLucas Stach dev_warn(pre->dev, "timeout waiting for PRE safe window\n");
24811aff4b4SLucas Stach return;
24911aff4b4SLucas Stach }
25011aff4b4SLucas Stach
25111aff4b4SLucas Stach val = readl(pre->regs + IPU_PRE_STORE_ENG_STATUS);
25211aff4b4SLucas Stach current_yblock =
25311aff4b4SLucas Stach (val >> IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT) &
25411aff4b4SLucas Stach IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK;
25511aff4b4SLucas Stach } while (current_yblock == 0 || current_yblock >= pre->safe_window_end);
25611aff4b4SLucas Stach
257d2a34232SLucas Stach writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET);
258d2a34232SLucas Stach }
259d2a34232SLucas Stach
ipu_pre_update_pending(struct ipu_pre * pre)2600a29b1abSLucas Stach bool ipu_pre_update_pending(struct ipu_pre *pre)
2610a29b1abSLucas Stach {
2620a29b1abSLucas Stach return !!(readl_relaxed(pre->regs + IPU_PRE_CTRL) &
2630a29b1abSLucas Stach IPU_PRE_CTRL_SDW_UPDATE);
2640a29b1abSLucas Stach }
2650a29b1abSLucas Stach
ipu_pre_get_baddr(struct ipu_pre * pre)266d2a34232SLucas Stach u32 ipu_pre_get_baddr(struct ipu_pre *pre)
267d2a34232SLucas Stach {
268d2a34232SLucas Stach return (u32)pre->buffer_paddr;
269d2a34232SLucas Stach }
270d2a34232SLucas Stach
ipu_pre_probe(struct platform_device * pdev)271d2a34232SLucas Stach static int ipu_pre_probe(struct platform_device *pdev)
272d2a34232SLucas Stach {
273d2a34232SLucas Stach struct device *dev = &pdev->dev;
274d2a34232SLucas Stach struct ipu_pre *pre;
275d2a34232SLucas Stach
276d2a34232SLucas Stach pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL);
277d2a34232SLucas Stach if (!pre)
278d2a34232SLucas Stach return -ENOMEM;
279d2a34232SLucas Stach
280*98935088SYangtao Li pre->regs = devm_platform_ioremap_resource(pdev, 0);
281d2a34232SLucas Stach if (IS_ERR(pre->regs))
282d2a34232SLucas Stach return PTR_ERR(pre->regs);
283d2a34232SLucas Stach
284d2a34232SLucas Stach pre->clk_axi = devm_clk_get(dev, "axi");
285d2a34232SLucas Stach if (IS_ERR(pre->clk_axi))
286d2a34232SLucas Stach return PTR_ERR(pre->clk_axi);
287d2a34232SLucas Stach
288d2a34232SLucas Stach pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0);
289d2a34232SLucas Stach if (!pre->iram)
290d2a34232SLucas Stach return -EPROBE_DEFER;
291d2a34232SLucas Stach
292d2a34232SLucas Stach /*
293d2a34232SLucas Stach * Allocate IRAM buffer with maximum size. This could be made dynamic,
294d2a34232SLucas Stach * but as there is no other user of this IRAM region and we can fit all
295d2a34232SLucas Stach * max sized buffers into it, there is no need yet.
296d2a34232SLucas Stach */
297d2a34232SLucas Stach pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH *
298d2a34232SLucas Stach IPU_PRE_NUM_SCANLINES * 4,
299d2a34232SLucas Stach &pre->buffer_paddr);
300d2a34232SLucas Stach if (!pre->buffer_virt)
301d2a34232SLucas Stach return -ENOMEM;
302d2a34232SLucas Stach
30347c298f7SLucas Stach clk_prepare_enable(pre->clk_axi);
30447c298f7SLucas Stach
305d2a34232SLucas Stach pre->dev = dev;
306d2a34232SLucas Stach platform_set_drvdata(pdev, pre);
307d2a34232SLucas Stach mutex_lock(&ipu_pre_list_mutex);
308d2a34232SLucas Stach list_add(&pre->list, &ipu_pre_list);
309d2a34232SLucas Stach available_pres++;
310d2a34232SLucas Stach mutex_unlock(&ipu_pre_list_mutex);
311d2a34232SLucas Stach
312d2a34232SLucas Stach return 0;
313d2a34232SLucas Stach }
314d2a34232SLucas Stach
ipu_pre_remove(struct platform_device * pdev)315d2a34232SLucas Stach static int ipu_pre_remove(struct platform_device *pdev)
316d2a34232SLucas Stach {
317d2a34232SLucas Stach struct ipu_pre *pre = platform_get_drvdata(pdev);
318d2a34232SLucas Stach
319d2a34232SLucas Stach mutex_lock(&ipu_pre_list_mutex);
320d2a34232SLucas Stach list_del(&pre->list);
321d2a34232SLucas Stach available_pres--;
322d2a34232SLucas Stach mutex_unlock(&ipu_pre_list_mutex);
323d2a34232SLucas Stach
32447c298f7SLucas Stach clk_disable_unprepare(pre->clk_axi);
32547c298f7SLucas Stach
326d2a34232SLucas Stach if (pre->buffer_virt)
327d2a34232SLucas Stach gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt,
328d2a34232SLucas Stach IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4);
329d2a34232SLucas Stach return 0;
330d2a34232SLucas Stach }
331d2a34232SLucas Stach
332d2a34232SLucas Stach static const struct of_device_id ipu_pre_dt_ids[] = {
333d2a34232SLucas Stach { .compatible = "fsl,imx6qp-pre", },
334d2a34232SLucas Stach { /* sentinel */ },
335d2a34232SLucas Stach };
336d2a34232SLucas Stach
337d2a34232SLucas Stach struct platform_driver ipu_pre_drv = {
338d2a34232SLucas Stach .probe = ipu_pre_probe,
339d2a34232SLucas Stach .remove = ipu_pre_remove,
340d2a34232SLucas Stach .driver = {
341d2a34232SLucas Stach .name = "imx-ipu-pre",
342d2a34232SLucas Stach .of_match_table = ipu_pre_dt_ids,
343d2a34232SLucas Stach },
344d2a34232SLucas Stach };
345