1 // SPDX-License-Identifier: GPL-2.0-only
22  * registers to acheive a fast co-oridinated rate change for all the CPU domain
36 #include <linux/clk-provider.h>
37 #include "clk-cpu.h"
71 	unsigned long timeout = jiffies + msecs_to_jiffies(10);  in wait_until_divider_stable()  local
76 	} while (time_before(jiffies, timeout));  in wait_until_divider_stable()
81 	pr_err("%s: timeout in divider stablization\n", __func__);  in wait_until_divider_stable()
91 	unsigned long timeout = jiffies + msecs_to_jiffies(10);  in wait_until_mux_stable()  local
96 	} while (time_before(jiffies, timeout));  in wait_until_mux_stable()
101 	pr_err("%s: re-parenting mux timed-out\n", __func__);  in wait_until_mux_stable()
148 /* handler for pre-rate change notification from parent clock */
152 	const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;  in exynos_cpuclk_pre_rate_change()
153 	unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);  in exynos_cpuclk_pre_rate_change()
159 	while ((cfg_data->prate * 1000) != ndata->new_rate) {  in exynos_cpuclk_pre_rate_change()
160 		if (cfg_data->prate == 0)  in exynos_cpuclk_pre_rate_change()
161 			return -EINVAL;  in exynos_cpuclk_pre_rate_change()
165 	spin_lock_irqsave(cpuclk->lock, flags);  in exynos_cpuclk_pre_rate_change()
168 	 * For the selected PLL clock frequency, get the pre-defined divider  in exynos_cpuclk_pre_rate_change()
172 	div0 = cfg_data->div0;  in exynos_cpuclk_pre_rate_change()
173 	if (cpuclk->flags & CLK_CPU_HAS_DIV1) {  in exynos_cpuclk_pre_rate_change()
174 		div1 = cfg_data->div1;  in exynos_cpuclk_pre_rate_change()
188 	if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {  in exynos_cpuclk_pre_rate_change()
189 		unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);  in exynos_cpuclk_pre_rate_change()
191 		alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;  in exynos_cpuclk_pre_rate_change()
194 		if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {  in exynos_cpuclk_pre_rate_change()
215 	if (cpuclk->flags & CLK_CPU_HAS_DIV1) {  in exynos_cpuclk_pre_rate_change()
221 	spin_unlock_irqrestore(cpuclk->lock, flags);  in exynos_cpuclk_pre_rate_change()
225 /* handler for post-rate change notification from parent clock */
229 	const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;  in exynos_cpuclk_post_rate_change()
235 	if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {  in exynos_cpuclk_post_rate_change()
236 		while ((cfg_data->prate * 1000) != ndata->new_rate) {  in exynos_cpuclk_post_rate_change()
237 			if (cfg_data->prate == 0)  in exynos_cpuclk_post_rate_change()
238 				return -EINVAL;  in exynos_cpuclk_post_rate_change()
243 	spin_lock_irqsave(cpuclk->lock, flags);  in exynos_cpuclk_post_rate_change()
250 	if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {  in exynos_cpuclk_post_rate_change()
251 		div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);  in exynos_cpuclk_post_rate_change()
256 	spin_unlock_irqrestore(cpuclk->lock, flags);  in exynos_cpuclk_post_rate_change()
276 /* handler for pre-rate change notification from parent clock */
280 	const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;  in exynos5433_cpuclk_pre_rate_change()
281 	unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);  in exynos5433_cpuclk_pre_rate_change()
287 	while ((cfg_data->prate * 1000) != ndata->new_rate) {  in exynos5433_cpuclk_pre_rate_change()
288 		if (cfg_data->prate == 0)  in exynos5433_cpuclk_pre_rate_change()
289 			return -EINVAL;  in exynos5433_cpuclk_pre_rate_change()
293 	spin_lock_irqsave(cpuclk->lock, flags);  in exynos5433_cpuclk_pre_rate_change()
296 	 * For the selected PLL clock frequency, get the pre-defined divider  in exynos5433_cpuclk_pre_rate_change()
299 	div0 = cfg_data->div0;  in exynos5433_cpuclk_pre_rate_change()
300 	div1 = cfg_data->div1;  in exynos5433_cpuclk_pre_rate_change()
310 	if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {  in exynos5433_cpuclk_pre_rate_change()
311 		unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);  in exynos5433_cpuclk_pre_rate_change()
313 		alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;  in exynos5433_cpuclk_pre_rate_change()
332 	spin_unlock_irqrestore(cpuclk->lock, flags);  in exynos5433_cpuclk_pre_rate_change()
336 /* handler for post-rate change notification from parent clock */
344 	spin_lock_irqsave(cpuclk->lock, flags);  in exynos5433_cpuclk_post_rate_change()
352 	spin_unlock_irqrestore(cpuclk->lock, flags);  in exynos5433_cpuclk_post_rate_change()
357  * This notifier function is called for the pre-rate and post-rate change
369 	base = cpuclk->ctrl_base;  in exynos_cpuclk_notifier_cb()
380  * This notifier function is called for the pre-rate and post-rate change
392 	base = cpuclk->ctrl_base;  in exynos5433_cpuclk_notifier_cb()
416 		return -EINVAL;  in exynos_register_cpu_clock()
421 		return -ENOMEM;  in exynos_register_cpu_clock()
431 	cpuclk->alt_parent = alt_parent;  in exynos_register_cpu_clock()
432 	cpuclk->hw.init = &init;  in exynos_register_cpu_clock()
433 	cpuclk->ctrl_base = ctx->reg_base + offset;  in exynos_register_cpu_clock()
434 	cpuclk->lock = &ctx->lock;  in exynos_register_cpu_clock()
435 	cpuclk->flags = flags;  in exynos_register_cpu_clock()
437 		cpuclk->clk_nb.notifier_call = exynos5433_cpuclk_notifier_cb;  in exynos_register_cpu_clock()
439 		cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;  in exynos_register_cpu_clock()
442 	ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);  in exynos_register_cpu_clock()
449 	cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL);  in exynos_register_cpu_clock()
450 	if (!cpuclk->cfg) {  in exynos_register_cpu_clock()
451 		ret = -ENOMEM;  in exynos_register_cpu_clock()
455 	ret = clk_hw_register(NULL, &cpuclk->hw);  in exynos_register_cpu_clock()
461 	samsung_clk_add_lookup(ctx, &cpuclk->hw, lookup_id);  in exynos_register_cpu_clock()
465 	kfree(cpuclk->cfg);  in exynos_register_cpu_clock()
467 	clk_notifier_unregister(parent->clk, &cpuclk->clk_nb);  in exynos_register_cpu_clock()
478 	struct clk_hw **hws = ctx->clk_data.hws;  in samsung_clk_register_cpu()
482 		for (num_cfgs = 0; list->cfg[num_cfgs].prate != 0; )  in samsung_clk_register_cpu()
485 		exynos_register_cpu_clock(ctx, list->id, list->name, hws[list->parent_id],  in samsung_clk_register_cpu()
486 				hws[list->alt_parent_id], list->offset, list->cfg, num_cfgs,  in samsung_clk_register_cpu()
487 				list->flags);  in samsung_clk_register_cpu()