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/openbmc/linux/drivers/clk/qcom/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
35 /* Skip if already enabled or in FSM mode */ in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
[all …]
H A Dclk-alpha-pll.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
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/openbmc/linux/drivers/clk/spear/
H A Dclk-vco-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * VCO-PLL clock implementation
9 #define pr_fmt(fmt) "clk-vco-pll: " fmt
11 #include <linux/clk-provider.h>
18 * DOC: VCO-PLL clock
20 * VCO and PLL rate are derived from following equations:
22 * In normal mode
25 * In Dithered mode
28 * pll_rate = pll/2^p
30 * vco and pll are very closely bound to each other, "vco needs to program:
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/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-pll.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 PLL Clock Generator Driver
8 * This driver is about to register JH7110 PLL clock generator and support ops.
9 * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2.
10 * Each PLL clocks work in integer mode or fraction mode by some dividers,
17 * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
22 #include <linux/clk-provider.h>
30 #include <dt-bindings/clock/starfive,jh7110-crg.h>
86 unsigned mode : 1; member
143 struct jh7110_pll_data pll[JH7110_PLLCLK_END]; member
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/openbmc/linux/drivers/clk/nuvoton/
H A Dclk-ma35d1-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chi-Fang Li <cfli0@nuvoton.com>
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
18 #include "clk-ma35d1.h"
20 /* PLL frequency limits */
36 /* bit fields for REG_CLK_PLL0CTL0, which is SMIC PLL design */
70 u8 mode; member
99 static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, unsigned long parent_rate) in ma35d1_calc_pll_freq() argument
111 if (mode == PLL_MODE_INT) { in ma35d1_calc_pll_freq()
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/openbmc/u-boot/arch/m68k/cpu/mcf5227x/
H A Dspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
44 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); in clock_enter_limp()
46 /* Enable Limp Mode */ in clock_enter_limp()
47 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_enter_limp()
51 * brief Exit Limp mode
52 * warning The PLL should be set and locked prior to exiting Limp mode
57 pll_t *pll = (pll_t *)MMAP_PLL; in clock_exit_limp() local
59 /* Exit Limp mode */ in clock_exit_limp()
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/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Dgeneric.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
14 #include <asm/mach-imx/sys_proto.h>
20 * get the system pll clock in Hz
23 * f = 2 * f_ref * --------------------
26 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) in imx_decode_pll() argument
28 unsigned int mfi = (pll >> 10) & 0xf; in imx_decode_pll()
29 unsigned int mfn = pll & 0x3ff; in imx_decode_pll()
30 unsigned int mfd = (pll >> 16) & 0x3ff; in imx_decode_pll()
31 unsigned int pd = (pll >> 26) & 0xf; in imx_decode_pll()
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/openbmc/linux/drivers/clk/zynqmp/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC PLL driver
5 * Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
16 * @clk_id: PLL clock ID
44 * zynqmp_pll_get_mode() - Get mode of PLL
45 * @hw: Handle between common and hardware-specific interfaces
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/openbmc/u-boot/arch/m68k/cpu/mcf532x/
H A Dspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2000-2003
7 * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
19 /* PLL min/max specifications */
53 pll_t *pll = (pll_t *)(MMAP_PLL); in get_sys_clock() local
56 /* Test to see if device is in LIMP mode */ in get_sys_clock()
57 if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) { in get_sys_clock()
58 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); in get_sys_clock()
67 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; in get_sys_clock()
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/openbmc/u-boot/arch/m68k/cpu/mcf5445x/
H A Dspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
45 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); in clock_enter_limp()
48 /* Enable Limp Mode */ in clock_enter_limp()
49 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_enter_limp()
53 * brief Exit Limp mode
54 * warning The PLL should be set and locked prior to exiting Limp mode
59 pll_t *pll = (pll_t *)MMAP_PLL; in clock_exit_limp() local
61 /* Exit Limp mode */ in clock_exit_limp()
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/openbmc/qemu/include/hw/misc/
H A Daspeed_scu.h9 * the COPYING file in the top-level directory.
19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"
23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"
24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
84 * arch/arm/mach-aspeed/include/mach/regs-scu.h
86 * Copyright (C) 2012-2020 ASPEED Technology Inc.
120 * SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC)
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/openbmc/linux/drivers/video/fbdev/aty/
H A Dradeon_base.c38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
240 /* these common regs are cleared before mode setting so they do not
263 static int default_dynclk = -2;
283 if (rinfo->no_schedule || oops_in_progress) in _radeon_msleep()
291 /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */ in radeon_pll_errata_after_index_slow()
298 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) { in radeon_pll_errata_after_data_slow()
302 if (rinfo->errata & CHIP_ERRATA_R300_CG) { in radeon_pll_errata_after_data_slow()
317 spin_lock_irqsave(&rinfo->reg_lock, flags); in _OUTREGP()
322 spin_unlock_irqrestore(&rinfo->reg_lock, flags); in _OUTREGP()
410 if (!rinfo->bios_seg) in radeon_unmap_ROM()
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsa8295p-adp.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11 #include <dt-bindings/spmi/spmi.h>
14 #include "sa8540p-pmics.dtsi"
18 compatible = "qcom,sa8295p-adp", "qcom,sa8540p";
25 stdout-path = "serial0:115200n8";
28 dp2-connector {
29 compatible = "dp-connector";
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/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32h7-rcc.txt6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32h743-rcc"
13 - reg: should be register base and length as documented in the
16 - #reset-cells: 1, see below
18 - #clock-cells : from common clock binding; shall be set to 1
20 - clocks: External oscillator clock phandle
21 - high speed external clock signal (HSE)
22 - low speed external clock signal (LSE)
23 - external I2S clock (I2S_CKIN)
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/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dadv7343.txt3 The ADV7343 are high speed, digital-to-analog video encoders in a 64-lead LQFP
4 package. Six high speed, 3.3 V, 11-bit video DACs provide support for composite
5 (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard
10 - compatible: Must be "adi,adv7343"
13 - adi,power-mode-sleep-mode: on enable the current consumption is reduced to
14 micro ampere level. All DACs and the internal PLL
16 - adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows
17 internal PLL 1 circuit to be powered down and the
19 - ad,adv7343-power-mode-dac: array configuring the power on/off DAC's 1..6,
22 - ad,adv7343-sd-config-dac-out: array configure SD DAC Output's 1 and 2, 0 = OFF
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/openbmc/linux/drivers/clk/bcm/
H A Dclk-iproc-armpll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
66 static unsigned int __get_fid(struct iproc_arm_pll *pll) in __get_fid() argument
71 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
80 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
84 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
88 pr_debug("%s: fid override %u->%u\n", __func__, fid, in __get_fid()
101 * - 25 MHz Crystal
102 * - System clock
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/openbmc/u-boot/drivers/video/sunxi/
H A Dlcdc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
6 * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
16 static int lcdc_get_clk_delay(const struct display_timing *mode, int tcon) in lcdc_get_clk_delay() argument
20 delay = mode->vfront_porch.typ + mode->vsync_len.typ + in lcdc_get_clk_delay()
21 mode->vback_porch.typ; in lcdc_get_clk_delay()
22 if (mode->flags & DISPLAY_FLAGS_INTERLACED) in lcdc_get_clk_delay()
25 delay -= 2; in lcdc_get_clk_delay()
33 writel(0, &lcdc->ctrl); /* Disable tcon */ in lcdc_init()
34 writel(0, &lcdc->int0); /* Disable all interrupts */ in lcdc_init()
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/openbmc/linux/drivers/gpu/drm/radeon/
H A Datombios_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
36 #include "atom-bits.h"
39 struct drm_display_mode *mode, in atombios_overscan_setup() argument
42 struct drm_device *dev = crtc->dev; in atombios_overscan_setup()
43 struct radeon_device *rdev = dev->dev_private; in atombios_overscan_setup()
51 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
53 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
[all …]
H A Dradeon_display.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
52 struct drm_device *dev = crtc->dev; in avivo_crtc_load_lut()
53 struct radeon_device *rdev = dev->dev_private; in avivo_crtc_load_lut()
57 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in avivo_crtc_load_lut()
58 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
60 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
61 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
62 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
64 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
65 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5341.txt6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
20 The driver can be used in "as is" mode, reading the current settings from the
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
36 "silabs,si5342" - Si5342 A/B/C/D
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/openbmc/linux/drivers/gpu/drm/stm/
H A Ddw_mipi_dsi-stm.c1 // SPDX-License-Identifier: GPL-2.0
32 #define WCFGR_DSIM BIT(0) /* DSI Mode */
39 #define WISR_PLLLS BIT(8) /* PLL Lock Status */
46 #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
47 #define WRPCR_PLLEN BIT(0) /* PLL ENable */
48 #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */
49 #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */
50 #define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */
73 /* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */
89 writel(val, dsi->base + reg); in dsi_write()
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/openbmc/u-boot/arch/m68k/cpu/mcf52x2/
H A Dspeed.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
17 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
21 pll_t *pll = (pll_t *) MMAP_PLL; in get_clocks() local
23 out_8(&pll->odr, CONFIG_SYS_PLL_ODR); in get_clocks()
24 out_8(&pll->fdr, CONFIG_SYS_PLL_FDR); in get_clocks()
34 /* Setup the PLL to run at the specified speed */ in get_clocks()
36 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
38 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
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/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_lvds.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
13 #include <linux/media-bus-format.h>
53 #define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */
54 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
88 return ioread32(lvds->mmio + reg); in rcar_lvds_read()
93 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
96 /* -----------------------------------------------------------------------------
97 * PLL Setup
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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/openbmc/linux/arch/mips/boot/dts/qca/
H A Dar9331.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
17 clocks = <&pll ATH79_CLK_CPU>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar7100-cpu-intc";
25 interrupt-controller;
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