1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2003 4 * Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 7 * Hayden Fraser (Hayden.Fraser@freescale.com) 8 */ 9 10 #include <common.h> 11 #include <asm/processor.h> 12 #include <asm/immap.h> 13 #include <asm/io.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ get_clocks(void)18int get_clocks (void) 19 { 20 #if defined(CONFIG_M5208) 21 pll_t *pll = (pll_t *) MMAP_PLL; 22 23 out_8(&pll->odr, CONFIG_SYS_PLL_ODR); 24 out_8(&pll->fdr, CONFIG_SYS_PLL_FDR); 25 #endif 26 27 #if defined(CONFIG_M5249) || defined(CONFIG_M5253) 28 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); 29 unsigned long pllcr; 30 31 #ifndef CONFIG_SYS_PLL_BYPASS 32 33 #ifdef CONFIG_M5249 34 /* Setup the PLL to run at the specified speed */ 35 #ifdef CONFIG_SYS_FAST_CLK 36 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ 37 #else 38 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ 39 #endif 40 #endif /* CONFIG_M5249 */ 41 42 #ifdef CONFIG_M5253 43 pllcr = CONFIG_SYS_PLLCR; 44 #endif /* CONFIG_M5253 */ 45 46 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ 47 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ 48 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ 49 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ 50 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ 51 udelay(0x20); /* Wait for a lock ... */ 52 #endif /* #ifndef CONFIG_SYS_PLL_BYPASS */ 53 54 #endif /* CONFIG_M5249 || CONFIG_M5253 */ 55 56 #if defined(CONFIG_M5275) 57 pll_t *pll = (pll_t *)(MMAP_PLL); 58 59 /* Setup PLL */ 60 out_be32(&pll->syncr, 0x01080000); 61 while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) 62 ; 63 out_be32(&pll->syncr, 0x01000000); 64 while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) 65 ; 66 #endif 67 68 gd->cpu_clk = CONFIG_SYS_CLK; 69 #if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ 70 defined(CONFIG_M5271) || defined(CONFIG_M5275) 71 gd->bus_clk = gd->cpu_clk / 2; 72 #else 73 gd->bus_clk = gd->cpu_clk; 74 #endif 75 76 #ifdef CONFIG_SYS_I2C_FSL 77 gd->arch.i2c1_clk = gd->bus_clk; 78 #ifdef CONFIG_SYS_I2C2_FSL_OFFSET 79 gd->arch.i2c2_clk = gd->bus_clk; 80 #endif 81 #endif 82 83 return (0); 84 } 85