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/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dst,stm32-pinctrl.txt4 controller. It controls the input/output settings on the available pins and
5 also provides ability to multiplex and configure the output of various on-chip
10 - compatible: value should be one of the following:
11 (a) "st,stm32f429-pinctrl"
12 (b) "st,stm32f746-pinctrl"
13 - #address-cells: The value of this property must be 1
14 - #size-cells : The value of this property must be 1
15 - ranges : defines mapping between pin controller node (parent) to
16 gpio-bank node (children).
17 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt65xx-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
13 The MediaTek's MT65xx Pin controller is used to control SoC pins.
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
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H A Dsunplus,sp7021-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Dvorkin Dmitry <dvorkin@tibbo.com>
12 - Wells Lu <wellslutw@gmail.com>
15 The Sunplus SP7021 pin controller is used to control SoC pins. Please
16 refer to pinctrl-bindings.txt in this directory for details of the common
19 SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All
20 are multiplexed with some special function pins. SP7021 has 3 types of
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H A Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
15 controller. It controls the input/output settings on the available pins and
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
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/openbmc/linux/drivers/pinctrl/nomadik/
H A Dpinctrl-abx500.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 /* pins alternate function */
34 * struct abx500_function - ABx500 pinctrl mux function
46 * struct abx500_pingroup - describes a ABx500 pin group
48 * @pins: an array of discrete physical pins used in this group, taken
49 * from the driver-local pin enumeration space
50 * @num_pins: the number of pins in this group array, i.e. the number of
51 * elements in .pins so we can iterate over that array
52 * @altsetting: the altsetting to apply to all pins in this group to
57 const unsigned int *pins; member
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H A Dpinctrl-nomadik.h1 /* SPDX-License-Identifier: GPL-2.0 */
66 * Used to reference an Other alternate-C function.
77 * struct prcm_gpio_altcx - Other alternate-C function
78 * @used: other alternate-C function availability
89 * struct prcm_gpio_altcx_pin_desc - Other alternate-C pin
91 * @altcx: array of other alternate-C[1-4] functions
99 * struct nmk_function - Nomadik pinctrl mux function
111 * struct nmk_pingroup - describes a Nomadik pin group
112 * @grp: Generic data of the pin group (name and pins)
113 * @altsetting: the altsetting to apply to all pins in this group to
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/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp157-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
10 pinctrl: pin-controller@50002000 {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "st,stm32mp157-pinctrl";
15 interrupt-parent = <&exti>;
17 pins-are-numbered;
20 gpio-controller;
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H A Dstm32h743-pinctrl.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/pinctrl/stm32h7-pinfunc.h>
47 pin-controller {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "st,stm32h743-pinctrl";
52 pins-are-numbered;
55 gpio-controller;
56 #gpio-cells = <2>;
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H A Dstm32f4-pinctrl.dtsi2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
45 #include <dt-bindings/mfd/stm32f4-rcc.h>
49 pinctrl: pin-controller {
50 #address-cells = <1>;
51 #size-cells = <1>;
53 interrupt-parent = <&exti>;
55 pins-are-numbered;
58 gpio-controller;
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H A Dstm32f746.dtsi2 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
3 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
7 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
9 * This file is dual-licensed: you can use it either under the terms
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
50 #include <dt-bindings/clock/stm32fx-clock.h>
51 #include <dt-bindings/mfd/stm32f7-rcc.h>
55 clk_hse: clk-hse {
56 #clock-cells = <0>;
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/openbmc/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra.h1 /* SPDX-License-Identifier: GPL-2.0-only */
47 /* argument: Integer, range is HW-dependant */
49 /* argument: Integer, range is HW-dependant */
51 /* argument: Integer, range is HW-dependant */
53 /* argument: Integer, range is HW-dependant */
55 /* argument: Integer, range is HW-dependant */
75 * struct tegra_function - Tegra pinctrl mux function
87 * struct tegra_pingroup - Tegra pin group
89 * @pins An array of pin IDs included in this pin group.
90 * @npins The number of entries in @pins.
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/openbmc/linux/arch/arm64/boot/dts/st/
H A Dstm32mp251.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
13 #address-cells = <1>;
14 #size-cells = <0>;
17 compatible = "arm,cortex-a35";
20 enable-method = "psci";
24 arm-pmu {
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/openbmc/u-boot/doc/device-tree-bindings/adc/
H A Dst,stm32-adc.txt3 STM32 ADC is a successive approximation analog-to-digital converter.
6 stored in a left-aligned or right-aligned 32-bit data register.
10 voltage goes beyond the user-defined, higher or lower thresholds.
16 - regular conversion can be done in sequence, running in background
17 - injected conversions have higher priority, and so have the ability to
22 -----------------------------------
24 - compatible: Should be one of:
25 "st,stm32f4-adc-core"
26 "st,stm32h7-adc-core"
27 "st,stm32mp1-adc-core"
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/openbmc/u-boot/drivers/misc/
H A Dali512x.c1 // SPDX-License-Identifier: GPL-2.0+
9 *----------------------------------------------------------------------
11 * Sysgo Real-Time Solutions GmbH
12 * Klein-Winternheim, Germany
13 *----------------------------------------------------------------------
139 /* huh? write 0xf2 twice - a typo in rolo in ali512x_set_uart()
197 * there may be some mis-understandings burried in here.
198 * -- Daniel daniel@omicron.se)
200 * There are 22 CIO pins numbered
201 * 10-17
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/openbmc/u-boot/cmd/
H A Dgpio.c2 * Control GPIO pins on the fly
4 * Copyright (c) 2008-2011 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
87 debug("GPIO device %s has no bits\n", dev->name); in do_gpio_status()
133 argc -= 2; in do_gpio()
136 if (argc > 0 && !strcmp(*argv, "-a")) { in do_gpio()
138 argc--; in do_gpio()
181 * Once all GPIO drivers are converted to driver model, we can change the in do_gpio()
182 * code here to use the GPIO uclass interface instead of the numbered in do_gpio()
198 if (ret && ret != -EBUSY) { in do_gpio()
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/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-snowball.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011 ST-Ericsson AB
6 /dts-v1/;
7 #include "ste-db9500.dtsi"
8 #include "ste-href-ab8500.dtsi"
9 #include "ste-href-family-pinctrl.dtsi"
13 compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500";
21 compatible = "simple-battery";
22 battery-type = "lithium-ion-polymer";
25 thermal-zones {
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/openbmc/linux/drivers/pinctrl/spear/
H A Dpinctrl-spear.h26 * struct spear_pmx_mode - SPEAr pmx mode
42 * struct spear_muxreg - SPEAr mux reg configuration
54 const unsigned *pins; member
85 .pins = __pins, \
92 * struct spear_modemux - SPEAr mode mux configuration
104 * struct spear_pingroup - SPEAr pin group configurations
106 * @pins: array containing pin numbers
107 * @npins: size of pins array
111 * A representation of a group of pins in the SPEAr pin controller. Each group
116 const unsigned *pins; member
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/openbmc/linux/Documentation/driver-api/gpio/
H A Dlegacy.rst13 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
14 digital signal. They are provided from many kinds of chip, and are familiar
21 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
22 non-dedicated pin can be configured as a GPIO; and most chips have at least
25 often have a few such pins to help with pin scarcity on SOCs; and there are
27 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
32 - Output values are writable (high=1, low=0). Some chips also have
34 value might be driven ... supporting "wire-OR" and similar schemes
37 - Input values are likewise readable (1, 0). Some chips support readback
38 of pins configured as "output", which is very useful in such "wire-OR"
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/openbmc/linux/drivers/net/ethernet/freescale/
H A Dfsl_pq_mdio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
9 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
71 * Per-device-type data. Each type of device tree node that we support gets
93 * control interfaces like onchip SERDES and are always tied to the local
94 * mdio pins, which may not be the same as system mdio bus, used for
100 struct fsl_pq_mdio_priv *priv = bus->priv; in fsl_pq_mdio_write()
101 struct fsl_pq_mii __iomem *regs = priv->regs; in fsl_pq_mdio_write()
105 iowrite32be((mii_id << 8) | regnum, &regs->miimadd); in fsl_pq_mdio_write()
108 iowrite32be(value, &regs->miimcon); in fsl_pq_mdio_write()
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/openbmc/linux/arch/alpha/kernel/
H A Dsys_cabriolet.c1 // SPDX-License-Identifier: GPL-2.0
43 int ofs = (irq - 16) / 8; in cabriolet_update_irq_hw()
50 cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq)); in cabriolet_enable_irq()
56 cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq); in cabriolet_disable_irq()
81 pld &= pld - 1; /* clear least bit set */ in cabriolet_device_interrupt()
114 if (request_irq(16 + 4, no_action, 0, "isa-cascade", NULL)) in common_init_irq()
115 pr_err("Failed to register isa-cascade interrupt\n"); in common_init_irq()
165 * the on-board NCR and Tulip chips. In the code below, I have used
169 * that's printed on the board. The interrupt pins from the PCI slots
170 * are wired into 3 interrupt summary registers at 0x804, 0x805 and
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/openbmc/linux/drivers/net/can/
H A Dti_hecc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
28 #include <linux/can/rx-offload.h>
36 #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
37 #define MAX_TX_PRIO 0x3F /* hardware value - do not change */
42 * for the mailbox logic to work. Top mailbox numbers are reserved for RX
55 #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1)
56 #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
60 * The remaining mailboxes are used for reception and are delivered
62 * changed while CAN-bus traffic is being received.
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/openbmc/linux/drivers/pinctrl/
H A Dpinmux.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
24 #include <linux/radix-tree.h>
38 const struct pinmux_ops *ops = pctldev->desc->pmxops; in pinmux_check_ops()
44 !ops->get_functions_count || in pinmux_check_ops()
45 !ops->get_function_name || in pinmux_check_ops()
46 !ops->get_function_groups || in pinmux_check_ops()
47 !ops->set_mux) { in pinmux_check_ops()
48 dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n"); in pinmux_check_ops()
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H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
62 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
77 return pctldev->desc->name; in pinctrl_dev_get_name()
83 return dev_name(pctldev->dev); in pinctrl_dev_get_devname()
89 return pctldev->driver_data; in pinctrl_dev_get_drvdata()
94 * get_pinctrl_dev_from_devname() - look up pin controller device
110 if (!strcmp(dev_name(pctldev->dev), devname)) { in get_pinctrl_dev_from_devname()
129 if (device_match_of_node(pctldev->dev, np)) { in get_pinctrl_dev_from_of_node()
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/openbmc/linux/arch/mips/include/asm/sgi/
H A Dheart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
7 * 2007-2015 Joshua Kinard <kumba@gentoo.org>
16 * There are 8 DIMM slots on an IP30 system
17 * board, which are grouped into four banks
27 * struct ip30_heart_regs - struct that maps IP30 HEART registers.
28 * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
29 * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
30 * @mem_refresh: HEART_MEM_REF - purpose unknown.
31 * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
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/openbmc/linux/drivers/usb/serial/
H A Dark3116.c1 // SPDX-License-Identifier: GPL-2.0+
9 * - implements a driver for the arkmicro ark3116 chipset (vendor=0x6547,
10 * productid=0x0232) (used in a datacable called KQ-U8A)
52 struct usb_device *dev = serial->dev; in is_irda()
53 if (le16_to_cpu(dev->descriptor.idVendor) == 0x18ec && in is_irda()
54 le16_to_cpu(dev->descriptor.idProduct) == 0x3118) in is_irda()
81 /* 0xfe 0x40 are magic values taken from original driver */ in ark3116_write_reg()
82 result = usb_control_msg(serial->dev, in ark3116_write_reg()
83 usb_sndctrlpipe(serial->dev, 0), in ark3116_write_reg()
96 /* 0xfe 0xc0 are magic values taken from original driver */ in ark3116_read_reg()
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