1340407d2SWells Lu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2340407d2SWells Lu# Copyright (C) Sunplus Co., Ltd. 3340407d2SWells Lu%YAML 1.2 4340407d2SWells Lu--- 5340407d2SWells Lu$id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml# 6340407d2SWells Lu$schema: http://devicetree.org/meta-schemas/core.yaml# 7340407d2SWells Lu 8dd3cb467SAndrew Lunntitle: Sunplus SP7021 Pin Controller 9340407d2SWells Lu 10340407d2SWells Lumaintainers: 11340407d2SWells Lu - Dvorkin Dmitry <dvorkin@tibbo.com> 12340407d2SWells Lu - Wells Lu <wellslutw@gmail.com> 13340407d2SWells Lu 14340407d2SWells Ludescription: | 15340407d2SWells Lu The Sunplus SP7021 pin controller is used to control SoC pins. Please 16340407d2SWells Lu refer to pinctrl-bindings.txt in this directory for details of the common 17340407d2SWells Lu pinctrl bindings used by client devices. 18340407d2SWells Lu 19340407d2SWells Lu SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All 20340407d2SWells Lu are multiplexed with some special function pins. SP7021 has 3 types of 21340407d2SWells Lu special function pins: 22340407d2SWells Lu 23340407d2SWells Lu (1) function-group pins: 24340407d2SWells Lu Ex 1 (SPI-NOR flash): 25340407d2SWells Lu If control-field SPI_FLASH_SEL is set to 1, GPIO 83, 84, 86 and 87 26340407d2SWells Lu will be pins of SPI-NOR flash. If it is set to 2, GPIO 76, 78, 79 27340407d2SWells Lu and 81 will be pins of SPI-NOR flash. 28340407d2SWells Lu 29340407d2SWells Lu Ex 2 (UART_0): 30340407d2SWells Lu If control-bit UA0_SEL is set to 1, GPIO 88 and 89 will be TX and 31340407d2SWells Lu RX pins of UART_0 (UART channel 0). 32340407d2SWells Lu 33340407d2SWells Lu Ex 3 (eMMC): 34340407d2SWells Lu If control-bit EMMC_SEL is set to 1, GPIO 72, 73, 74, 75, 76, 77, 35340407d2SWells Lu 78, 79, 80, 81 will be pins of an eMMC device. 36340407d2SWells Lu 37340407d2SWells Lu Properties "function" and "groups" are used to select function-group 38340407d2SWells Lu pins. 39340407d2SWells Lu 40340407d2SWells Lu (2) fully pin-mux (like phone exchange mux) pins: 41340407d2SWells Lu GPIO 8 to 71 are 'fully pin-mux' pins. Any pins of peripherals of 42340407d2SWells Lu SP7021 (ex: UART_1, UART_2, UART_3, UART_4, I2C_0, I2C_1, and etc.) 43340407d2SWells Lu can be routed to any pins of fully pin-mux pins. 44340407d2SWells Lu 45340407d2SWells Lu Ex 1 (UART channel 1): 46340407d2SWells Lu If control-field UA1_TX_SEL is set to 3, TX pin of UART_1 will be 47340407d2SWells Lu routed to GPIO 10 (3 - 1 + 8 = 10). 48340407d2SWells Lu If control-field UA1_RX_SEL is set to 4, RX pin of UART_1 will be 49340407d2SWells Lu routed to GPIO 11 (4 - 1 + 8 = 11). 50340407d2SWells Lu If control-field UA1_RTS_SEL is set to 5, RTS pin of UART_1 will 51340407d2SWells Lu be routed to GPIO 12 (5 - 1 + 8 = 12). 52340407d2SWells Lu If control-field UA1_CTS_SEL is set to 6, CTS pin of UART_1 will 53340407d2SWells Lu be routed to GPIO 13 (6 - 1 + 8 = 13). 54340407d2SWells Lu 55340407d2SWells Lu Ex 2 (I2C channel 0): 56340407d2SWells Lu If control-field I2C0_CLK_SEL is set to 20, CLK pin of I2C_0 will 57340407d2SWells Lu be routed to GPIO 27 (20 - 1 + 8 = 27). 58340407d2SWells Lu If control-field I2C0_DATA_SEL is set to 21, DATA pin of I2C_0 59340407d2SWells Lu will be routed to GPIO 28 (21 - 1 + 9 = 28). 60340407d2SWells Lu 61340407d2SWells Lu Totally, SP7021 has 120 peripheral pins. The peripheral pins can be 62340407d2SWells Lu routed to any of 64 'fully pin-mux' pins. 63340407d2SWells Lu 64340407d2SWells Lu (3) I/O processor pins 65340407d2SWells Lu SP7021 has a built-in I/O processor. 66340407d2SWells Lu Any GPIO pins (GPIO 0 to 98) can be set to pins of I/O processor. 67340407d2SWells Lu 68340407d2SWells Lu Vendor property "sunplus,pins" is used to select "fully pin-mux" pins, 69340407d2SWells Lu "I/O processor pins" and "digital GPIO" pins. 70340407d2SWells Lu 71340407d2SWells Lu The device node of pin controller of Sunplus SP7021 has following 72340407d2SWells Lu properties. 73340407d2SWells Lu 74340407d2SWells Luproperties: 75340407d2SWells Lu compatible: 76340407d2SWells Lu const: sunplus,sp7021-pctl 77340407d2SWells Lu 78340407d2SWells Lu gpio-controller: true 79340407d2SWells Lu 80340407d2SWells Lu '#gpio-cells': 81340407d2SWells Lu const: 2 82340407d2SWells Lu 83340407d2SWells Lu reg: 84340407d2SWells Lu items: 85340407d2SWells Lu - description: the MOON2 registers 86340407d2SWells Lu - description: the GPIOXT registers 87340407d2SWells Lu - description: the FIRST registers 88340407d2SWells Lu - description: the MOON1 registers 89340407d2SWells Lu 90340407d2SWells Lu reg-names: 91340407d2SWells Lu items: 92340407d2SWells Lu - const: moon2 93340407d2SWells Lu - const: gpioxt 94340407d2SWells Lu - const: first 95340407d2SWells Lu - const: moon1 96340407d2SWells Lu 97340407d2SWells Lu clocks: 98340407d2SWells Lu maxItems: 1 99340407d2SWells Lu 100340407d2SWells Lu resets: 101340407d2SWells Lu maxItems: 1 102340407d2SWells Lu 103340407d2SWells LupatternProperties: 104340407d2SWells Lu '-pins$': 105340407d2SWells Lu type: object 106340407d2SWells Lu description: | 107340407d2SWells Lu A pinctrl node should contain at least one subnodes representing the 108340407d2SWells Lu pins or function-pins group available on the machine. Each subnode 109340407d2SWells Lu will list the pins it needs, and how they should be configured. 110340407d2SWells Lu 111340407d2SWells Lu Pinctrl node's client devices use subnodes for desired pin 112340407d2SWells Lu configuration. Client device subnodes use below standard properties. 113340407d2SWells Lu $ref: pinmux-node.yaml# 114340407d2SWells Lu 115340407d2SWells Lu properties: 116340407d2SWells Lu sunplus,pins: 117340407d2SWells Lu description: | 118340407d2SWells Lu Define 'sunplus,pins' which are used by pinctrl node's client 119340407d2SWells Lu device. 120340407d2SWells Lu 121340407d2SWells Lu It consists of one or more integers which represents the config 122340407d2SWells Lu setting for corresponding pin. Each integer defines a individual 123340407d2SWells Lu pin in which: 124340407d2SWells Lu 125340407d2SWells Lu Bit 32~24: defines GPIO number. Its range is 0 ~ 98. 126340407d2SWells Lu Bit 23~16: defines types: (1) fully pin-mux pins 127340407d2SWells Lu (2) IO processor pins 128340407d2SWells Lu (3) digital GPIO pins 129340407d2SWells Lu Bit 15~8: defines pins of peripherals (which are defined in 130340407d2SWells Lu 'include/dt-binging/pinctrl/sppctl.h'). 131340407d2SWells Lu Bit 7~0: defines types or initial-state of digital GPIO pins. 132340407d2SWells Lu 133340407d2SWells Lu Please use macro SPPCTL_IOPAD to define the integers for pins. 134340407d2SWells Lu 135340407d2SWells Lu $ref: /schemas/types.yaml#/definitions/uint32-array 136340407d2SWells Lu 137340407d2SWells Lu function: 138340407d2SWells Lu description: | 139340407d2SWells Lu Define pin-function which is used by pinctrl node's client device. 140340407d2SWells Lu The name should be one of string in the following enumeration. 141*49cd1dd1SRob Herring $ref: /schemas/types.yaml#/definitions/string 142340407d2SWells Lu enum: [ SPI_FLASH, SPI_FLASH_4BIT, SPI_NAND, CARD0_EMMC, SD_CARD, 143340407d2SWells Lu UA0, FPGA_IFX, HDMI_TX, LCDIF, USB0_OTG, USB1_OTG ] 144340407d2SWells Lu 145340407d2SWells Lu groups: 146340407d2SWells Lu description: | 147340407d2SWells Lu Define pin-group in a specified pin-function. 148340407d2SWells Lu The name should be one of string in the following enumeration. 149*49cd1dd1SRob Herring $ref: /schemas/types.yaml#/definitions/string 150340407d2SWells Lu enum: [ SPI_FLASH1, SPI_FLASH2, SPI_FLASH_4BIT1, SPI_FLASH_4BIT2, 151340407d2SWells Lu SPI_NAND, CARD0_EMMC, SD_CARD, UA0, FPGA_IFX, HDMI_TX1, 152340407d2SWells Lu HDMI_TX2, HDMI_TX3, LCDIF, USB0_OTG, USB1_OTG ] 153340407d2SWells Lu 154340407d2SWells Lu sunplus,zerofunc: 155340407d2SWells Lu description: | 156340407d2SWells Lu This is a vendor specific property. It is used to disable pins 157340407d2SWells Lu which are not used by pinctrl node's client device. 158340407d2SWells Lu Some pins may be enabled by boot-loader. We can use this 159340407d2SWells Lu property to disable them. 160340407d2SWells Lu $ref: /schemas/types.yaml#/definitions/uint32-array 161340407d2SWells Lu 162340407d2SWells Lu additionalProperties: false 163340407d2SWells Lu 164340407d2SWells Lu allOf: 165340407d2SWells Lu - if: 166340407d2SWells Lu properties: 167340407d2SWells Lu function: 168340407d2SWells Lu enum: 169340407d2SWells Lu - SPI_FLASH 170340407d2SWells Lu then: 171340407d2SWells Lu properties: 172340407d2SWells Lu groups: 173340407d2SWells Lu enum: 174340407d2SWells Lu - SPI_FLASH1 175340407d2SWells Lu - SPI_FLASH2 176340407d2SWells Lu - if: 177340407d2SWells Lu properties: 178340407d2SWells Lu function: 179340407d2SWells Lu enum: 180340407d2SWells Lu - SPI_FLASH_4BIT 181340407d2SWells Lu then: 182340407d2SWells Lu properties: 183340407d2SWells Lu groups: 184340407d2SWells Lu enum: 185340407d2SWells Lu - SPI_FLASH_4BIT1 186340407d2SWells Lu - SPI_FLASH_4BIT2 187340407d2SWells Lu - if: 188340407d2SWells Lu properties: 189340407d2SWells Lu function: 190340407d2SWells Lu enum: 191340407d2SWells Lu - SPI_NAND 192340407d2SWells Lu then: 193340407d2SWells Lu properties: 194340407d2SWells Lu groups: 195340407d2SWells Lu enum: 196340407d2SWells Lu - SPI_NAND 197340407d2SWells Lu - if: 198340407d2SWells Lu properties: 199340407d2SWells Lu function: 200340407d2SWells Lu enum: 201340407d2SWells Lu - CARD0_EMMC 202340407d2SWells Lu then: 203340407d2SWells Lu properties: 204340407d2SWells Lu groups: 205340407d2SWells Lu enum: 206340407d2SWells Lu - CARD0_EMMC 207340407d2SWells Lu - if: 208340407d2SWells Lu properties: 209340407d2SWells Lu function: 210340407d2SWells Lu enum: 211340407d2SWells Lu - SD_CARD 212340407d2SWells Lu then: 213340407d2SWells Lu properties: 214340407d2SWells Lu groups: 215340407d2SWells Lu enum: 216340407d2SWells Lu - SD_CARD 217340407d2SWells Lu - if: 218340407d2SWells Lu properties: 219340407d2SWells Lu function: 220340407d2SWells Lu enum: 221340407d2SWells Lu - UA0 222340407d2SWells Lu then: 223340407d2SWells Lu properties: 224340407d2SWells Lu groups: 225340407d2SWells Lu enum: 226340407d2SWells Lu - UA0 227340407d2SWells Lu - if: 228340407d2SWells Lu properties: 229340407d2SWells Lu function: 230340407d2SWells Lu enum: 231340407d2SWells Lu - FPGA_IFX 232340407d2SWells Lu then: 233340407d2SWells Lu properties: 234340407d2SWells Lu groups: 235340407d2SWells Lu enum: 236340407d2SWells Lu - FPGA_IFX 237340407d2SWells Lu - if: 238340407d2SWells Lu properties: 239340407d2SWells Lu function: 240340407d2SWells Lu enum: 241340407d2SWells Lu - HDMI_TX 242340407d2SWells Lu then: 243340407d2SWells Lu properties: 244340407d2SWells Lu groups: 245340407d2SWells Lu enum: 246340407d2SWells Lu - HDMI_TX1 247340407d2SWells Lu - HDMI_TX2 248340407d2SWells Lu - HDMI_TX3 249340407d2SWells Lu - if: 250340407d2SWells Lu properties: 251340407d2SWells Lu function: 252340407d2SWells Lu enum: 253340407d2SWells Lu - LCDIF 254340407d2SWells Lu then: 255340407d2SWells Lu properties: 256340407d2SWells Lu groups: 257340407d2SWells Lu enum: 258340407d2SWells Lu - LCDIF 259340407d2SWells Lu - if: 260340407d2SWells Lu properties: 261340407d2SWells Lu function: 262340407d2SWells Lu enum: 263340407d2SWells Lu - USB0_OTG 264340407d2SWells Lu then: 265340407d2SWells Lu properties: 266340407d2SWells Lu groups: 267340407d2SWells Lu enum: 268340407d2SWells Lu - USB0_OTG 269340407d2SWells Lu - if: 270340407d2SWells Lu properties: 271340407d2SWells Lu function: 272340407d2SWells Lu enum: 273340407d2SWells Lu - USB1_OTG 274340407d2SWells Lu then: 275340407d2SWells Lu properties: 276340407d2SWells Lu groups: 277340407d2SWells Lu enum: 278340407d2SWells Lu - USB1_OTG 279340407d2SWells Lu 280340407d2SWells Lurequired: 281340407d2SWells Lu - compatible 282340407d2SWells Lu - reg 283340407d2SWells Lu - reg-names 284340407d2SWells Lu - "#gpio-cells" 285340407d2SWells Lu - gpio-controller 286340407d2SWells Lu - clocks 287340407d2SWells Lu - resets 288340407d2SWells Lu 289340407d2SWells LuadditionalProperties: false 290340407d2SWells Lu 2910e9e3132SKrzysztof KozlowskiallOf: 292*49cd1dd1SRob Herring - $ref: pinctrl.yaml# 2930e9e3132SKrzysztof Kozlowski 294340407d2SWells Luexamples: 295340407d2SWells Lu - | 296340407d2SWells Lu #include <dt-bindings/pinctrl/sppctl-sp7021.h> 297340407d2SWells Lu 2980e9e3132SKrzysztof Kozlowski pinctrl@9c000100 { 299340407d2SWells Lu compatible = "sunplus,sp7021-pctl"; 300340407d2SWells Lu reg = <0x9c000100 0x100>, <0x9c000300 0x100>, 301340407d2SWells Lu <0x9c0032e4 0x1c>, <0x9c000080 0x20>; 302340407d2SWells Lu reg-names = "moon2", "gpioxt", "first", "moon1"; 303340407d2SWells Lu gpio-controller; 304340407d2SWells Lu #gpio-cells = <2>; 305340407d2SWells Lu clocks = <&clkc 0x83>; 306340407d2SWells Lu resets = <&rstc 0x73>; 307340407d2SWells Lu 308340407d2SWells Lu uart0-pins { 309340407d2SWells Lu function = "UA0"; 310340407d2SWells Lu groups = "UA0"; 311340407d2SWells Lu }; 312340407d2SWells Lu 313340407d2SWells Lu spinand0-pins { 314340407d2SWells Lu function = "SPI_NAND"; 315340407d2SWells Lu groups = "SPI_NAND"; 316340407d2SWells Lu }; 317340407d2SWells Lu 318340407d2SWells Lu uart1-pins { 319340407d2SWells Lu sunplus,pins = < 320340407d2SWells Lu SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) 321340407d2SWells Lu SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) 322340407d2SWells Lu >; 323340407d2SWells Lu }; 324340407d2SWells Lu 325340407d2SWells Lu uart2-pins { 326340407d2SWells Lu sunplus,pins = < 327340407d2SWells Lu SPPCTL_IOPAD(20, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) 328340407d2SWells Lu SPPCTL_IOPAD(21, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) 329340407d2SWells Lu SPPCTL_IOPAD(22, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0) 330340407d2SWells Lu SPPCTL_IOPAD(23, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0) 331340407d2SWells Lu >; 332340407d2SWells Lu }; 333340407d2SWells Lu 334340407d2SWells Lu emmc-pins { 335340407d2SWells Lu function = "CARD0_EMMC"; 336340407d2SWells Lu groups = "CARD0_EMMC"; 337340407d2SWells Lu }; 338340407d2SWells Lu 339340407d2SWells Lu sdcard-pins { 340340407d2SWells Lu function = "SD_CARD"; 341340407d2SWells Lu groups = "SD_CARD"; 342340407d2SWells Lu sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >; 343340407d2SWells Lu }; 344340407d2SWells Lu 345340407d2SWells Lu hdmi_A_tx1-pins { 346340407d2SWells Lu function = "HDMI_TX"; 347340407d2SWells Lu groups = "HDMI_TX1"; 348340407d2SWells Lu }; 349340407d2SWells Lu hdmi_A_tx2-pins { 350340407d2SWells Lu function = "HDMI_TX"; 351340407d2SWells Lu groups = "HDMI_TX2"; 352340407d2SWells Lu }; 353340407d2SWells Lu hdmi_A_tx3-pins { 354340407d2SWells Lu function = "HDMI_TX"; 355340407d2SWells Lu groups = "HDMI_TX3"; 356340407d2SWells Lu }; 357340407d2SWells Lu 358340407d2SWells Lu ethernet-pins { 359340407d2SWells Lu sunplus,pins = < 360340407d2SWells Lu SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0) 361340407d2SWells Lu SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0) 362340407d2SWells Lu SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0) 363340407d2SWells Lu SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0) 364340407d2SWells Lu SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0) 365340407d2SWells Lu SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0) 366340407d2SWells Lu SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0) 367340407d2SWells Lu SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0) 368340407d2SWells Lu SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0) 369340407d2SWells Lu >; 370340407d2SWells Lu sunplus,zerofunc = < 371340407d2SWells Lu MUXF_L2SW_LED_FLASH0 372340407d2SWells Lu MUXF_L2SW_LED_ON0 373340407d2SWells Lu MUXF_L2SW_P0_MAC_RMII_RXER 374340407d2SWells Lu >; 375340407d2SWells Lu }; 376340407d2SWells Lu }; 377340407d2SWells Lu... 378