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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dfsl-enetc.txt1 * ENETC ethernet device tree bindings
5 below device tree bindings.
9 - reg : Specifies PCIe Device Number and Function
11 to parent node bindings.
12 - compatible : Should be "fsl,enetc".
14 1. The ENETC external port is connected to a MDIO configurable phy
18 In this case, the ENETC node should include a "mdio" sub-node
19 that in turn should contain the "ethernet-phy" node describing the
20 external phy. Below properties are required, their bindings
21 already defined in Documentation/devicetree/bindings/net/ethernet.txt or
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H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dti,dp83867.txt1 * Texas Instruments - dp83867 Giga bit ethernet phy
4 - reg - The ID number for the phy, usually a small integer
5 - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
7 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
9 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
11 - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
13 - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
15 - ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h
18 Default child nodes are standard Ethernet PHY device
19 nodes as described in doc/devicetree/bindings/net/ethernet.txt
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-lpc18xx-usb-otg.txt1 NXP LPC18xx/43xx internal USB OTG PHY binding
2 ---------------------------------------------
4 This file contains documentation for the internal USB OTG PHY found
8 - compatible : must be "nxp,lpc1850-usb-otg-phy"
9 - clocks : must be exactly one entry
10 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
11 - #phy-cells : must be 0 for this phy
12 See: Documentation/devicetree/bindings/phy/phy-bindings.txt
14 The phy node must be a child of the creg syscon node.
18 compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
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H A Drockchip,inno-usb2phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USB2.0 phy with inno IP block
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3128-usb2phy
17 - rockchip,rk3228-usb2phy
18 - rockchip,rk3308-usb2phy
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H A Dallwinner,sun9i-a80-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun9i-a80-usb-phy
25 - maxItems: 1
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H A Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8 SoC series PCIe PHY
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
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H A Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Torrent SD0801 PHY
10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
12 PHY also supports multilink multiprotocol combinations including protocols
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
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H A Dpistachio-usb-phy.txt1 IMG Pistachio USB PHY
5 --------------------
6 - compatible: Must be "img,pistachio-usb-phy".
7 - #phy-cells: Must be 0. See ./phy-bindings.txt for details.
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clock/clock-bindings.txt for details.
10 - clock-names: Must include "usb_phy".
11 - img,cr-top: Must contain a phandle to the CR_TOP syscon node.
12 - img,refclk: Indicates the reference clock source for the USB PHY.
13 See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
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H A Dphy-hisi-inno-usb2.txt1 Device tree bindings for HiSilicon INNO USB2 PHY
4 - compatible: Should be one of the following strings:
5 "hisilicon,inno-usb2-phy",
6 "hisilicon,hi3798cv200-usb2-phy".
7 - reg: Should be the address space for PHY configuration register in peripheral
9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
13 - #address-cells: Must be 1.
14 - #size-cells: Must be 0.
16 The INNO USB2 PHY device should be a child node of peripheral controller that
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H A Dqcom,snps-eusb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SNPS eUSB2 phy controller
10 - Abel Vesa <abel.vesa@linaro.org>
17 const: qcom,sm8550-snps-eusb2-phy
22 "#phy-cells":
27 - description: ref
29 clock-names:
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H A Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
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H A Dallwinner,suniv-f1c100s-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner F1C100s USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,suniv-f1c100s-usb-phy
22 description: PHY Control registers
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H A Dallwinner,sun8i-v3s-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-v3s-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner V3s USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-v3s-usb-phy
22 - description: PHY Control registers
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H A Dphy-hi3798cv200-combphy.txt1 HiSilicon STB PCIE/SATA/USB3 PHY
4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
19 - hisilicon,mode-select-bits: If the phy device support mode select,
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H A Dqcom,qusb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm QUSB2 phy controller
11 - Wesley Cheng <quic_wcheng@quicinc.com>
19 - items:
20 - enum:
21 - qcom,ipq6018-qusb2-phy
22 - qcom,ipq8074-qusb2-phy
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H A Dallwinner,sun50i-a64-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A64 USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun20i-d1-usb-phy
20 - allwinner,sun50i-a64-usb-phy
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
15 sets, clock and PHY.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Ddwc3-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Piyush Mehta <piyush.mehta@amd.com>
15 - enum:
16 - xlnx,zynqmp-dwc3
17 - xlnx,versal-dwc3
21 "#address-cells":
24 "#size-cells":
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H A Dti,keystone-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Roger Quadros <rogerq@kernel.org>
15 - enum:
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
22 '#address-cells':
25 '#size-cells':
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H A Drockchip,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 Phy documentation is provided in the following places.
17 USB2.0 PHY
18 Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
20 Type-C PHY
21 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
24 - $ref: snps,dwc3.yaml#
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dnxp,imx-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
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/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
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/openbmc/linux/arch/mips/boot/dts/mscc/
H A Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
12 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 stdout-path = "serial0:115200n8";
25 phy_int_pins: phy-int-pins {
30 phy_load_save_pins: phy-load-save-pins {
42 pinctrl-names = "default";
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/openbmc/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
19 - rockchip,rk3568-pcie3-phy-grf
20 - rockchip,rk3568-pipe-grf
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